Project Overview TRS High Level Architecture Specification - - PowerPoint PPT Presentation

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Feb 26, 2024 116 likes •165 views

MIT9904-04 Malleable Architectures for Adaptive Computing Arvind, Rudolph and Devadas Project Overview TRS High Level Architecture Specification Language and Synthesis ISA Cache Malleable Architectures Specification

SLIDE 1

NTT - MIT Research Collaboration — Bi-Annual Report, January 1 – June 30, 2000

MIT9904-04 Malleable Architectures for Adaptive Computing

Arvind, Rudolph and Devadas

Project Overview

– High Level Architecture Specification Language and Synthesis

Malleable Architectures

– Arch. Specific ISA – Malleable Caches

Cache Specification ISA Specification TRS Compiler Custom Embedded Microprocessor Application ¥Stream ¥Real-Time ¥Multimedia

SLIDE 2

NTT - MIT Research Collaboration — Bi-Annual Report, January 1 – June 30, 2000

MIT9904-04 Malleable Architectures for Adaptive Computing

Arvind, Rudolph and Devadas

Progress Through June 2000

Column Cache Implementation

– Dedicated SRAM for embedded applications – Partitioned Cache for real-time applications

Adaptation Schemes for Multiprocessing
Curious Caching

– Initial Investigation

Column Cache ISA w/ cache control inst. TRS Compiler Custom Embedded Microprocessor Application ¥Stream ¥Real-Time ¥Multimedia

SLIDE 3

NTT - MIT Research Collaboration — Bi-Annual Report, January 1 – June 30, 2000

MIT9904-04 Malleable Architectures for Adaptive Computing

Arvind, Rudolph and Devadas

Research Plan for the Next Six Months

Apply Technology to

– Speech Processing (SLS) – Image Understanding

Analyze Other Apps
Architectural Description