Product Development Dilemma Product Development Dilemma - - PDF document

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Product Development Dilemma Product Development Dilemma - - PDF document

Nov 10, 2022 102 likes •175 views

A Revolutionary Solution for A Revolutionary Solution for Unified RF System and Circuit Unified RF System and Circuit Design Design EDP-2002 Conference Monterey, California April 21-23 James Spoto President and CEO AWR Product

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SLIDE 1

1 EDP-2002 Conference Monterey, California April 21-23

James Spoto President and CEO AWR

A Revolutionary Solution for A Revolutionary Solution for Unified RF System and Circuit Unified RF System and Circuit Design Design

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  • Product Development Dilemma

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SLIDE 2

2

  • Technology (µm)

100 10 1.0 0.5 .35 .25 .18.15 .1 20 40 60 80 Ft (GHz) .13 0.45 - 1 GHz >4 GHz 10 Gb/s 2 GHz 2.5 Gb/s C M O S BiCMOS 200 >10 GHz 40 Gb/s I n G a P H B T I n P H B T GaAs-pHEMT

  • SiGe BiCMOS

Ft ~ 70GHz @ 0.35m Ft ~ 120GHz @ 0.18m Si BiCMOS Ft ~ 30GHz @ 0.35m Si CMOS Ft ~ 15GHz @ 0.5m Ft ~ 25GHz @ 0.35m Ft ~ 35GHz @ 0.25m Ft ~ 50GHz @ 0.18m InGaP HBT Ft ~ 85GHz @ 1.0m SiGe BiCMOS InP-pHEMT

  • Schematic

Capture Circuit Simulation & Waveform Tool Analog P&R & Layout Editor DRC, LVS & Extraction Tools

AWR EDA Platform

Symbols & Component Descriptions Spice Models Interconnect & Passive Models Device Generators & Layout Options LVS, DRC, Ext Tech Files

Foundry Kit Representations Foundry Kit Representations Foundry Kit Representations

Design Platform Architecture Design Platform Architecture

Design Capture & Synthesis Exploration, Optimization & Analysis Physical Design Final Design Verification

Application Specific Circuit Design Flow Application Specific Circuit Design Flow Application Specific Circuit Design Flow

Block Arch & Component Descriptions Parameterized Systems Models Component Footprint & Chip/MCM/PCB P&R Chip/Board Verification

Application Specific IP and System Design Flow Application Specific IP and Application Specific IP and System Design Flow System Design Flow

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SLIDE 3

3

  • Application Specific Design Solutions

Application Specific Design Solutions

Design Capture & Synthesis Circuit & System Simulation & Analysis IC Layout & Chip/PCB P&R Interface DRC, LVS & Extraction Tools

AWR EDA Platform

  • InP

InP InP SiGe SiGe SiGe RF CMOS RF CMOS RF CMOS InGaP InGaP InGaP

  • Microwave

Microwave Microwave RF RF RF MIMIC MIMIC MIMIC RF PCB RF PCB RF PCB RFIC RFIC RFIC Optical IC Optical Optical IC IC

  • Satellite

Satellite Satellite 802.11/ Bluetooth 802.11/ 802.11/ Bluetooth Bluetooth LMDS/ MMDS LMDS/ LMDS/ MMDS MMDS Wideband CDMA Wideband Wideband CDMA CDMA OCxxx OCxxx OCxxx

  • DCVS
V= ID= 0.93 V VB B1 DC VS V= ID= 3.97 V VC C1 LTU NER Zo= Ang= Mag= ID= 50 Ohm 170.3 Deg 0.505 TU1 LTUNE R Zo= Ang = Mag= ID = 50 Oh m 155 Deg 0.255 TU2 DC RF RF & DC 1 2 3 BIA STEE ID=X1 DC RF RF & DC 1 2 3 BIA STEE ID=X2 I_METER ID=AMP2 I_MET ER ID=AMP1 V_MET ER ID=VM1 V_METER ID=VM2 V_ME TER ID =VM3 I_MET ER ID=AMP3 V_METER ID=V M4 I_ ME TER ID=AMP4 V _METER ID =VM5 I_METER ID=AMP5 C B E 1 2 3 SU BCKT N ET= ID= "BF G1981" S1 PORT _PS1 PS tep= PS top= PS tar t= Z= P= 1 d B 10 dBm
  • 40 dBm
50 Ohm 1. PORT Z= P= 50 Ohm 2.

AWGN PSD= ID=

  • 30 dB

A2 R D IQ 1 2 3 4 5 RCVR ID= A3 TP ID= MSIG TP ID= AMP TP ID= CHNL TP ID= RCVR MPSK_SRC CDNG= CTRFRQ= PTYP= PWR= MOD= ID= Binary 0 MHz

  • Avg. Power
  • 24.3 dB

8-PSK A1 NL_HB NET= ID= "High Power BJT Amp" S1

  • 20
  • 10

10 20

Constellations

  • 20
  • 10

10 20

IQ[TP.RCVR,100,1] System Diagram 1 IQ[TP.AMP,100,1] System Diagram 1
  • 8e-006
  • 4e-006

4e-006 8e-006 Frequency (MHz) Power Spectrums

  • 150
  • 100
  • 50

50

DB(PWR_SPEC[TP.MSIG,1024,5]) (dBm) System Diagram 1 DB(PWR_SPEC[TP.AMP,1024,5]) (dBm) System Diagram 1 DB(PWR_SPEC[TP.CHNL,256,5]) (dBm) System Diagram 1

2 4 6 8 10 BER 1e-005 .0001 .001 .01 .1 1

BER[BER.3] QPSK QPSK_BERREF[BER.3,0,0] QPSK 1.0 1.0
  • 1.0
10.0 10.0
  • 1
. 5.0 5.0
  • 5.0
2.0 2.0
  • 2.0
3.0 3 .
  • 3.0
4.0 4.0
  • 4.0
0.2 0.2
  • 0.2
0.4 . 4
  • .
4 0.6 0.6
  • 0.6
0.8 . 8
  • .
8

Smith Chart

Swp Max 7.3GHz Swp Min 6.7GHz

S[1,1] S[2,2]

  • 30
30 Power (dBm) Voltage Gain
  • 10
  • 5
5 10 15 Voltage Gain Available Voltage G ain 20 40 60 80 98 Frequency (GHz)

Spectrum

  • 50
  • 30
  • 10

10 20 Power (dBm) Output Power (dBm) Delivered Input Power (dBm)

Systems Level

(Time Domain)

Circuit Level

(Freq Domain)

  • Spec Synthesis
  • Test Bench
  • Behavioral Model
  • Characterization
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SLIDE 4

4

A Unique Product Architecture A Unique Product Architecture

T P ID = 2 T P ID = 3 T P ID = 4 Q A M _ S R C R A T E = C T R F R Q = O L V L T Y P = O U T L V L = M O D = ID = _ D R A T E 1 9 M H z S ym b
  • l
E n e r g y P W R d B 1 6
  • Q
A M A 1 R D IQ 1 2 3 4 5 Q A M _ R X ID = A 2 BER B E R S W P T Y P = S W P V A R = ID = A u to P B A S E 5 A W G N P S D = ID =
  • 4
9 + P A D J d B A 3 T P ID = 6 P H A S E S H F T = ID = 9 9 D e g A 4 N L _ S N E T = ID = "A M P 1 9 S y s te m s T e s t" S 1 SRC MEAS V S A S W P V A R = ID = M 1 P B A S E = s w e e p ( s te p p e d (
  • 6
,-2 ,2 ) ) P W R = P B A S E + P A D J P A D J =
  • 1
*lo g 1 ( _ Z )

Traditional EDA Systems

Netlists Datafiles

AWR EDA System

Common Database

T P ID = 2 T P ID = 3 T P ID = 4 Q A M _ S R C R A T E = C T R F R Q = O L V L T Y P = O U T L V L = M O D = ID = _ D R A T E 1 9 M H z S ym b
  • l
E n e r g y P W R d B 1 6
  • Q
A M A 1 R D IQ 1 2 3 4 5 Q A M _ R X ID = A 2 BER B E R S W P T Y P = S W P V A R = ID = A u to P B A S E 5 A W G N P S D = ID =
  • 4
9 + P A D J d B A 3 T P ID = 6 P H A S E S H F T = ID = 9 9 D e g A 4 N L _ S N E T = ID = "A M P 1 9 S y s te m s T e s t" S 1 SRC MEAS V S A S W P V A R = ID = M 1 P B A S E = s w e e p ( s te p p e d (
  • 6
,-2 ,2 ) ) P W R = P B A S E + P A D J P A D J =
  • 1
*lo g 1 ( _ Z )

Robust Dependency Management Robust Dependency Management

All dependency relationships are managed in a uniform manner by the environment Since objects can cache state,

  • nly objects that change will

require updating

with Incremental Computation with Incremental Computation

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SLIDE 5

5

TP ID = 2 T P ID = 3 TP ID = 4 QA M _S R C R A TE = C T R F RQ = O L VLT YP = O U TL VL = M OD = ID = _ DR A TE 1 900 M H z S ym bo l En ergy P W R d B 1 6-Q AM A 1 R D IQ 1 2 3 4 5 Q AM _ R X ID = A 2 BER B E R S WP TY P= S WP VAR = ID = A uto P BASE 5 AW G N PS D = ID =

  • 4

9 +P AD J dB A3 T P ID= 6 PH ASE SH FT = ID = 99 D eg A4 N L _S N ET = ID = " AM P1 90 0 Sys tem s T est" S 1 SRC MEAS VSA S W P VAR = ID = M 1 P BA SE = sw ee p(ste p ped (-60 ,-2 0,2)) P W R =PB AS E+ PAD J P AD J =-1 0*log1 0(_Z0 )

CAP C= ID= 1e4 pF C1 CAP C= ID= 1e4 pF C2 CAP C= ID = 1e4 pF C3 RES R= ID= 4000 Ohm R1 RES R= ID= 5300 Ohm R2 RES R= ID= 225 Ohm R3 CAP C= ID= 0.91 pF C4 IND L= ID= 9.34 nH L1 CAP C= ID= 1.27 pF C5 IND L= ID= 0.8 nH L2 RES R= ID= 250 Ohm R4 RES R= ID= 630 Ohm R5 TLIN F0= EL= Z0= ID= 1900 MHz 64 D eg 50 Ohm TL1 TLIN F0= EL= Z0= ID= 1900 MHz 49.5 Deg 50 Ohm TL2 TLIN F0= EL= Z0= ID= 2000 M Hz 90 Deg 50 Ohm TL3 DCVS V= ID = BiasVolts V V1 V_METER ID= VM1 V_METER ID=VM2 S C B E 1 2 3 4 GBJT ID= GP1 1 2 SUBCKT NET= ID= "Digital Phase Shifter" S1 PORT Z= P= 50 Ohm 2 PORT_PS1 PStep= PStop= PStart= Z= P= 2 dB 0 dBm
  • 60 dBm
50 Ohm 1

Systems Level

(Time Domain)

Circuit Level

(Non-Linear Freq domain)

  • 40
  • 35
  • 30
  • 25
  • 20
  • 15
  • 10

Power (dBm)

AM_AM

  • 22.97
  • 17.97
  • 12.97
  • 7.97
  • 2.97

0.4046

BiasVolt=2.55 BiasVolt=2.4 BiasVolt=2.7

  • 40
  • 35
  • 30
  • 25
  • 20
  • 15
  • 10

Power (dBm)

AM_PM

  • 120
  • 100
  • 80
  • 60
  • 40
  • 30

BiasVolt=2.55 BiasVolt=2.7 BiasVolt=2.4

1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

  • 40 -35 -30 -25 -20 -15 -10

Symbol Error Rate

Input Power dBm

BiasVolt=2.55 BiasVolt=2.7 BiasVolt=2.4

1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

  • 40 -35 -30 -25 -20 -15 -10

Symbol Error Rate

Input Power dBm

BiasVolt=2.55 BiasVolt=2.7 BiasVolt=2.4

  • 1.5
  • 0.5

0.5 1.5

Constellation

  • 1.5
  • 0.5

0.5 1.5

  • 1.5
  • 0.5

0.5 1.5

IQ[TP.2,100,0] (L) IQ[TP.4,100,0] (R)

BiasVolt=2.55 Input pwr=-22dBm

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SLIDE 6

6

Summary Summary

  • Explosion in High-Freq applications, technologies and

associated Communications product opportunities

  • Comms product development cost and schedules are

impaired by the disconnects between Analog/RF system and circuit design

  • AWR is bridging this gap with a revolutionary new

Comms design solution that seamlessly integrates the system and circuit design process