Processors Zhishan Guo Department of Computer Science, UNC Chapel - PowerPoint PPT Presentation

MC Scheduling on Varying-Speed Processors Zhishan Guo Department of Computer Science, UNC Chapel Hill Dagstuhl 15121

Other Dimensions of Uncertainty -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip.

Other Dimensions of Uncertainty -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick.

Other Dimensions of Uncertainty -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick. • GALS: Globally Asynchronous Locally Synchronous – locally synchronous modules that communicate asynchronously – local clocks may be paused, stretched, or data-driven

Other Dimensions of Uncertainty -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick. • GALS: Globally Asynchronous Locally Synchronous – locally synchronous modules that communicate asynchronously – local clocks may be paused, stretched, or data-driven • Battery stretching (Dynamic frequency scaling ) – Clock rates (and voltage) are reduced…

Model - Varying-Speed Processor Clock frequency time

Model - Varying-Speed Processor Clock frequency 1 ρ time Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ

Model - Varying-Speed Processor Clock frequency Trigger - Mode Switch 1 ρ time Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ

Relationship with prior work • Multi-WCET task model (previous works) • J i - (a i , d i , [c iHI , c iLO ], χ i ) c iHI • Execution speed = 1 c iLO t • Varying-speed model ? • J i - (a i , d i , c i , χ i ), s n , s d c i • E.g., t s(t) s(t) s(t) 1 1 1 c i / s d c i / s n 0.5 0.5 0.5 c i c i c i 0 0 0 t t t A slower processor can be transformed into longer WCET

The uniprocessor world is so beautiful… Multi-WCET Varying-speed Job Set, OCBP, w/ monitoring: Table+LP, O(n 2 ) later, Opt! 2 criticality s=1.618 levels w/o monitoring: Similar, smaller * speed-up O(n 2 ) Job Set, OCBP more levels MC-EDF Dominates OCBP, MC-EDF? Task Set EDF-VD Fluid: Opt! s = 1.333 Limited preemption: Similar No loss when combining multi-WCET and varying-speed

but…

For Multiprocessor… • We now have m processors instead of one… • Degraded mode (heterogeneous) • A system with m processors is in degraded mode at a given instant t if there exists at least one processor executing at the speed in the range of [s,1)?

For Multiprocessor… • We now have m processors instead of one… • Degraded mode (heterogeneous) • A system with m processors is in degraded mode at a given instant t if there exists at least one processor executing at the speed in the range of [s,1)? • A system with m processors is in degraded mode at a given instant t if the average executing speed is in the range of [s,1).

For Multiprocessor… • We now have m processors instead of one… • Degraded mode (heterogeneous) • A system with m processors is in degraded mode at a given instant t if there exists at least one processor executing at the speed in the range of [s,1)? • A system with m processors is in degraded mode at a given instant t if the average executing speed is in the range of [s,1). • Be specific about the number of processors that are executing at the speed in the range of [s,1), and [0,s)?

Alessandro Biondi, Alessandra Melani, Mauro Marinoni, Marco Di Natale, Giorgio Buttazzo, Combination Exact Interference of Adaptive Variable-Rate Tasks Under Fixed-Priority Scheduling , ECRTS 2014 • Example: Adaptive Variable-Rate Tasks – The task activation is triggered at specific rotation angles – Varying rotation speeds lead to varying WCETs & periods • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – …

Thank you! Zhishan Guo zsguo@cs.unc.edu

References • [1] S. Baruah, H. Li and L. Stougie. Towards the design of certifiable mixed- criticality systems. RTAS2010. • [2] H. Li and S. Baruah. Global mixed-criticality scheduling on multiprocessors. IEEE ECRTS 2012. • [3] Dario Socci, et al. Mixed Critical Earliest Deadline First. ECRTS 2013. • [4] S. Baruah and Z. Guo. Scheduling mixed-criticality implicit-deadline sporadic task systems upon a varying-speed processor. RTSS 2014. • [5] — . Mixed-criticality scheduling upon varying-speed processors. IEEE RTSS 2013. • [6] Z. Guo and S. Baruah. Mixed-criticality scheduling upon varying-speed multiprocessors. Leibniz Transactions on Embedded Systems, 1(2): 3:1 - 3:19, 2014. • [7] — . The concurrent consideration of uncertainty in WCETs and processor speeds in mixed-criticality systems. Under submission. • [8] — . Mixed-criticality scheduling upon varying-speed multiprocessors. DASC 2014. • [9] — . Mixed-criticality scheduling upon unmonitored unreliable processors. SIES 2013.

m=2 For Multiprocessor… s n = 1 s d = 0.5 • More constraints need to be added… I a i c i d i χ i J LO 0 2 2 LO s(t) J HI1 0 2 3 HI J HI2 0 2 4 HI J HI1 t 0 2 4 S s(t) Intervals [0,2) [2,3) [3,4) J LO 2 0 0 J HI1 J HI1 1 1 0 t 0 2 4 J HI2 1 0 1

m=2 For Multiprocessor… s n = 1 s d = 0.5 • More constraints need to be added… I a i c i d i χ i Necessary and Sufficient J LO 0 2 2 LO J HI1 0 2 4 HI J HI2 0 2 4 HI S Intervals [0,2) [2,3) [3,4) J LO 2 0 0 J HI1 1 0.5 0.5 J HI2 1 0.5 0.5

m=2 For Multiprocessor… s n = 1 s d = 0.5 • Mapping a LP solution to a schedule… I a i c i d i χ i J LO J LO 0 2 2 LO s(t) J HI1 0 2 4 HI J HI2 0 2 4 HI 1 t 0 2 4 S s(t) Intervals [0,2) [2,3) [3,4) J LO 2 0 0 2 J HI1 1 0.5 0.5 t 0 2 4 J HI2 1 0.5 0.5

m=2 For Multiprocessor… s n = 1 s d = 0.5 • Mapping a LP solution to a schedule… I a i c i d i χ i J LO 0 2 2 LO 2 s(t) J HI1 0 2 4 HI J HI2 0 2 4 HI 1 t 0 2 4 S s(t) Intervals [0,2) [2,3) [3,4) J J LO 2 0 0 L O J HI1 1 0.5 0.5 t 0 2 4 J HI2 1 0.5 0.5