Processors Zhishan Guo Department of Computer Science, UNC Chapel - - PowerPoint PPT Presentation

MC Scheduling on Varying-Speed Processors

Zhishan Guo Department of Computer Science, UNC Chapel Hill Dagstuhl 15121

Other Dimensions of Uncertainty -- CPU Speeds

• Advanced hardware features

– Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip.

Other Dimensions of Uncertainty -- CPU Speeds

• Advanced hardware features

– Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick.

Other Dimensions of Uncertainty -- CPU Speeds

• Advanced hardware features

– Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick.

• GALS: Globally Asynchronous Locally Synchronous

– locally synchronous modules that communicate asynchronously – local clocks may be paused, stretched, or data-driven

Other Dimensions of Uncertainty -- CPU Speeds

• Advanced hardware features

– Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick.

• GALS: Globally Asynchronous Locally Synchronous

– locally synchronous modules that communicate asynchronously – local clocks may be paused, stretched, or data-driven

• Battery stretching (Dynamic frequency scaling )

– Clock rates (and voltage) are reduced…

Model - Varying-Speed Processor

Clock frequency time

time Clock frequency

ρ 1

Processor speed ≥ 1 Processor speed < 1, but ≥ ρ Processor speed < ρ

Model - Varying-Speed Processor

Model - Varying-Speed Processor

time Clock frequency

ρ 1

Processor speed ≥ 1 Processor speed < 1, but ≥ ρ Processor speed < ρ

Trigger - Mode Switch

Relationship with prior work

• Multi-WCET task model (previous works)
• Ji - (ai, di, [ciHI, ciLO], χi)
• Execution speed = 1
• Varying-speed model
• Ji - (ai, di, ci, χi), sn, sd
• E.g.,

ciLO ciHI t ci t ? t s(t) 1 0.5 ci

ci/sd

t 1 0.5 ci s(t)

ci/sn

t 1 0.5 ci s(t)

A slower processor can be transformed into longer WCET

The uniprocessor world is so beautiful…

Multi-WCET Varying-speed

Job Set, 2 criticality levels OCBP, s=1.618 w/ monitoring: Table+LP, O(n2) later, Opt! w/o monitoring: Similar, smaller* speed-up Job Set, more levels OCBP MC-EDF O(n2) Dominates OCBP, MC-EDF? Task Set EDF-VD s = 1.333 Fluid: Opt! Limited preemption: Similar No loss when combining multi-WCET and varying-speed

but…

For Multiprocessor…

• We now have m processors instead of one…
• Degraded mode (heterogeneous)
• A system with m processors is in degraded mode at a given

instant t if there exists at least one processor executing at the speed in the range of [s,1)?

For Multiprocessor…

• We now have m processors instead of one…
• Degraded mode (heterogeneous)
• A system with m processors is in degraded mode at a given

instant t if there exists at least one processor executing at the speed in the range of [s,1)?

• A system with m processors is in degraded mode at a given

instant t if the average executing speed is in the range of [s,1).

For Multiprocessor…

• We now have m processors instead of one…
• Degraded mode (heterogeneous)
• A system with m processors is in degraded mode at a given

instant t if there exists at least one processor executing at the speed in the range of [s,1)?

• A system with m processors is in degraded mode at a given

instant t if the average executing speed is in the range of [s,1).

• Be specific about the number of processors that are

executing at the speed in the range of [s,1), and [0,s)?

Combination

• Example: Adaptive Variable-Rate Tasks

– The task activation is triggered at specific rotation angles – Varying rotation speeds lead to varying WCETs & periods

• Multiple dimensions to such MC modeling

– upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – …

Alessandro Biondi, Alessandra Melani, Mauro Marinoni, Marco Di Natale, Giorgio Buttazzo, Exact Interference of Adaptive Variable-Rate Tasks Under Fixed-Priority Scheduling, ECRTS 2014

Thank you!

Zhishan Guo zsguo@cs.unc.edu

References

• [1] S. Baruah, H. Li and L. Stougie. Towards the design of certifiable mixed-

criticality systems. RTAS2010.

• [2] H. Li and S. Baruah. Global mixed-criticality scheduling on multiprocessors. IEEE

ECRTS 2012.

• [3] Dario Socci, et al. Mixed Critical Earliest Deadline First. ECRTS 2013.
• [4] S. Baruah and Z. Guo. Scheduling mixed-criticality implicit-deadline sporadic

task systems upon a varying-speed processor. RTSS 2014.

• [5] —. Mixed-criticality scheduling upon varying-speed processors. IEEE RTSS 2013.
• [6] Z. Guo and S. Baruah. Mixed-criticality scheduling upon varying-speed
• multiprocessors. Leibniz Transactions on Embedded Systems, 1(2): 3:1 - 3:19, 2014.
• [7] —. The concurrent consideration of uncertainty in WCETs and processor speeds

in mixed-criticality systems. Under submission.

• [8] —. Mixed-criticality scheduling upon varying-speed multiprocessors. DASC 2014.
• [9] —. Mixed-criticality scheduling upon unmonitored unreliable processors. SIES

2013.

For Multiprocessor…

• More constraints need to be added…

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 1 JHI2 1 1

S

I ai ci di χi JLO 2 2 LO JHI1 2 3 HI JHI2 2 4 HI

t 2 4

s(t) JHI1

t 2 4

s(t) JHI1

m=2 sn = 1 sd = 0.5

For Multiprocessor…

• More constraints need to be added…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI Necessary and Sufficient

For Multiprocessor…

• Mapping a LP solution to a schedule…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI

t 2 4

s(t)

1

t 2 4

s(t)

2

JLO

2

For Multiprocessor…

• Mapping a LP solution to a schedule…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI

t 2 4

s(t)

1

t 2 4

s(t) J

L O