processors for new highly informative experiments in space O. - PowerPoint PPT Presentation

НАУЧНО - ИССЛЕДОВАТЕЛЬСКИЙ ИНСТИТУТ СИСТЕМНЫХ ИССЛЕДОВАНИЙ (НИИСИ РАН) The special radiation-hardened processors for new highly informative experiments in space O. Serdin, А. Аn tonov, A. Dubrovsky, E. Novogilov, A. Zuev SRISA, serdin@cs.niisi.ras.ru

Three basic branches  1Х1:  Development ASIC  Software: and board:  CMOS 0,5 мкм  Real-time OS « Baget »  CMOS 0,35 мкм  Microprocessors,  Software for  SOI 0,5 мкм  Peripherial controllers, testing and SRAM …  SOI 0,35 мкм debugging  Development board,  SOI 0,25 мкм board for testing chips  Board for GAMMA-400 2

Microprocessors « KOMDIV » KOMDIV - 32 1 Х 1 SOI 0 , 5 um 1 Х 1 SOI 0 , 35 um 1 Х 1 SOI 0 , 25 um « Micron » SOI 024 CMOS 0 , 18 мкм 1907 VM 014 1907 VM 056 9011 VA 016 5890 VG 1 Т 1 Х 1 CMOS 1 Х 1 CMOS 0 , 5 um 0 , 35 um 5890 VM 1 Т 1900 VM 2 Т 1907 VM 044 1 890 VM 1 Т 1 890VM2T 5890 VE 1 Т 1907 VM 038 1907 VM 066 1907VK016 Plan 1907 VM 014 1907 VM 038 1 Х 1 CMOS CMOS 0 , 18 um 1907 VM 028 1907 VM 028 0 , 35 um KOMDIV - 64 19 90 VM 3 Т 1890 VM 7 Y Fault-tolerant:  CMOS 65 nm 1890 VM 8 Y 5890VM 1Т,  1900VM 2Т , 1 Х 1 CMOS 0 , 35 um CMOS 65 nm CMOS 0 , 18 um 1907VM038, 1890 VM 9 Y 1 890 VM 5 F 1890 VM 6 Y 1907VM014, 1907VM044 , 1907VM028, : 1907VM066, Microprocessor controller - - 1907VK016  - Soc SIP : 3

1907VM044 system-on-chip 0.25 μ m SOI CMOS  66 MHz  KOMDIV 32-bit,  Local TMR  Redundant SpaceWire interface controller  Redundant MIL STD 1553B interface  3 real time timers  SRAM controller  ROM controller  GPIO  2 RS-232 controllers  SPI  JTAG  4 GAMMA-400 scientific data acquisition system

1907VM044 OCP Controller 32 bit+ECC SRAM CPU ROM SRAM, PROM CPU OCP flash CPU OCP hub OCP SWpaceWire SW x2 SW OCP Interrupt GPIO SPI JTAG controller UART 1553B Timer 32x 5

Fault-tolerant  DICE-cell based cache memory  Parity bit (1 per byte) for cache memory  Hamming error correcting code for the built-in MIL-STD 1553 DICE-based memory  DICE-cells in register files with Hamming code protection (13,8) hardware scrubbing  SECDED for external memory  Hardware possibility of using SRAM in TMR mode  Spatial separation of neighboring bits (protection from MBU)  “guaranteed boot” from ROM  Local TMR  MBIST  TID: >200 krad (Si)  SEL free 6

Multiport switch Serial RapidIO 1907KX018 0.25 μ m SOI CMOS  is used for the connection of various  switches and systems-on-chip 6 RapidIO ports, the transferring  environment is configured independently: LP-Serial 4X or 1X  Maximum transferring speed is 1.25 Gbit/sec (per line) It has the routing table for each port,  performance control system, built-in error- correcting block The switch can directly connect up to 256  devices in the system Individual routing tables allows to flexibly  configure the transferring of data packages. The performance control system is used for  the defining of characteristics of data flow in channel, overload detection, the localization of locking. 7

1907VM038 System on chip – 128-bit DSP   >2 GFLOPS @ 100 MHz  >2 Gbit/s to external memory Architecture:   32-bit control core  128-bit computational co-processor  SPI, DDRII, RS232, RapidIO 8

Multiport switch SpaceWire with embedded processor 1907VM056 Frequency – 100 М Hz  9

1907VM066 Correlation Register ALU file SOI «Мi cron »  SRAM Rad-hard 32-bit microprocessor  Interrupt PCI controller with coprocessor proccesing and CPU controller compare data image for navigation Memory Arbiter HUB controller Arbiter and on-board systems SpaceWire Serial RapidIO Switch Controller 4 pcs.  UСС, В 3,3 4 pcs.  Frequency , М Hz > 100  Power consumption @ 100М Hz, W < 6 Timers UART I2C EJTAG SPI GPIO 1533B  Case CPGA 407 pins 3 pcs 2 pcs 10 10

1907VK016 Register ALU file SRAM 128 KB Interrupt CPU controller TMR Memory Arbiter controller Arbiter HUB SpaceWire Switch 4 pcs. Timers UART SPI GPIO 1533B 3 pcs 2 pcs 2 pcs. 32 pcs. 2 pcs.  Fault-tolerant microcontroller with TMR 11 11

9011V А016 1667 РА 014 D[39:32] < > D[7:0] SRA A[18:0] A[18:0] M CS1 1907 ВМ 056 CE# OE1 VSUB OE# VSUB5 ОЗУ / ППЗУ WE4 WE# FOF ОЗУ / ППЗУ < > DATA[39:0] CPU 1667 РА 014 ADR[26:0] D[31:24] ACK CS[3:0] < > D[7:0] SRA OE[3:0] A[18:0] A[18:0] WE[4:0] M BE[3:0] CS1 SpaceWire SpaceWire CE# OE1 VSUB OE# VSUB4 WE3 RS-232 RS-232 WE# FOF CAN CAN 1667 РА 014 D[23:16] JTAG JTAG < > D[7:0] SRA A[18:0] Интерфейс Интерфейс A[18:0] M ГОСТ Р 52070 ГОСТ Р 52070 Разовые команды CS1 CE# OE1 VSUB OE# VSUB3 Системные SPI WE2 WE# FOF Служебные Служебные 1667 РА 014 D[15:8] < > D[7:0] SRA A[18:0] 5576 ХС 8 Т A[18:0] M Пользовательские Пользовательские выводы выводы CS1 CE# OE1 VSUB < > IO[182:0] OE# CLOK[1:0] VSUB2 FPGA WE1 WE# FOF INPUT[3:0] JTAG 1667 РА 014 JTAG D[7:0] Системные Системные < > D[7:0] SRA A[18:0] A[18:0] M  Processor 100 МГц CS1 CE# OE1 VSUB OE# VSUB1 WE0 WE# FOF  SRAM 2 М B with correction WE[4:0] OE[3:0] BE[3:0] CS[3:0] D[39:0] A[26:0] FOF  FPGA 50 000 gates 12 12

Developing boards  Central p rocessor unit for SSNI “GAMMA - 400” based on 1907VM038  Control unit for SSNI “GAMMA - 400” based on 1907VM044  Switch Serial RapidIO based on 1907KX018 for OpenVPX systems  Switch SpaceWire based on 1907VM056 for OpenVPX systems  Central processor unit based on 1907VM028 for OpenVPX systems  Central processor unit based on 1907ВМ066 in form factor PC-104  Peripherial module with interface 1533B in form factor PC-104  Performance central processor board :  Based on 1907ВМ028 – 0,1 Gops на 64 -bit operand  Based on 1907ВМ038 – up to 2 GFlops на 32 -bit operand  Performance computer up to 2-8 GFlops on 32-bit operand  Throughput interprocessor channels:  Up to 6 channels Seraial RapidIO, 1 Gbit/s; up to 6 channels SPACEWIRE, 200 Mbit/s; 13 13

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