[PPT] - processors for new highly informative experiments in space O. PowerPoint Presentation

SLIDE 1

НАУЧНО-ИССЛЕДОВАТЕЛЬСКИЙ ИНСТИТУТ СИСТЕМНЫХ ИССЛЕДОВАНИЙ (НИИСИ РАН)

The special radiation-hardened processors for new highly informative experiments in space

O. Serdin, А. Аntonov, A. Dubrovsky, E. Novogilov,
A. Zuev

SRISA, serdin@cs.niisi.ras.ru

SLIDE 2

2

Three basic branches

 Development ASIC

and board:

 Microprocessors,  Peripherial controllers,

SRAM…

 Development board,

board for testing chips

 Board for GAMMA-400

 1Х1:

 CMOS 0,5 мкм  CMOS 0,35 мкм  SOI 0,5 мкм  SOI 0,35 мкм  SOI 0,25 мкм

 Software:

 Real-time OS

«Baget»

 Software for

testing and debugging

SLIDE 3

3

Microprocessors «KOMDIV»



Fault-tolerant:



5890VM1Т, 1900VM2Т, 1907VM038, 1907VM014, 1907VM044, 1907VM028, 1907VM066,



1907VK016

1 Х 1 SOI 0 , 25 um

KOMDIV -

32

CMOS 0 , 18 um CMOS 0 , 18 um

Plan « Micron » SOI 024 1 Х 1 SOI 0 , 35 um 1 Х 1 SOI 0 , 5 um

1 Х 1

CMOS , 35 um

1 Х 1

CMOS , 5 um

5890 VE 1 Т

1 890 VM 1 Т

5890 VG 1 Т

CMOS , 18

мкм

Microprocessor Soc controller SIP

1907 VM 014 1907 VM 038 1907 VM 028

1 Х 1 CMOS

, 35 um

19 90 VM 3 Т 1890 VM 7 Y

1 Х 1 CMOS , 35 um

1 890 VM 5 F

CMOS 65 nm

1890 VM 8 Y

CMOS 65 nm

1890 VM 9 Y

1 890VM2T

5890 VM 1 Т

1900 VM 2 Т

1907 VM 038

1907 VM 044 1907 VM 028

1907 VM 066 9011 VA 016 1907 VM 056

1907VK016

1907 VM 014 1890 VM 6 Y

KOMDIV -

64

:

:

SLIDE 4

GAMMA-400 scientific data acquisition system

4

1907VM044 system-on-chip



0.25 μm SOI CMOS



66 MHz



KOMDIV 32-bit,



Local TMR



Redundant SpaceWire interface controller



Redundant MIL STD 1553B interface



3 real time timers



SRAM controller



ROM controller



GPIO



2 RS-232 controllers



SPI



JTAG

SLIDE 5

5

1907VM044

CPU CPU CPU OCP hub SW SW

Controller SRAM, flash

SRAM ROM PROM OCP OCP OCP 32 bit+ECC SWpaceWire x2

Interrupt controller UART Timer GPIO SPI JTAG 1553B

OCP 32x

SLIDE 6

6

Fault-tolerant

 DICE-cell based cache memory  Parity bit (1 per byte) for cache memory  Hamming error correcting code for the built-in MIL-STD 1553

DICE-based memory

 DICE-cells in register files with Hamming code protection

(13,8) hardware scrubbing

 SECDED for external memory  Hardware possibility of using SRAM in TMR mode  Spatial separation of neighboring bits (protection from MBU)  “guaranteed boot” from ROM  Local TMR  MBIST  TID: >200 krad (Si)  SEL free

SLIDE 7

Multiport switch Serial RapidIO 1907KX018



0.25 μm SOI CMOS



is used for the connection of various switches and systems-on-chip



6 RapidIO ports, the transferring environment is configured independently: LP-Serial 4X or 1X



Maximum transferring speed is 1.25 Gbit/sec (per line)



It has the routing table for each port, performance control system, built-in error- correcting block



The switch can directly connect up to 256 devices in the system



Individual routing tables allows to flexibly configure the transferring of data packages.



The performance control system is used for the defining of characteristics of data flow in channel, overload detection, the localization of locking. 7

SLIDE 8

8

1907VM038



System on chip – 128-bit DSP

 >2 GFLOPS @ 100 MHz  >2 Gbit/s to external memory



Architecture:

 32-bit control core  128-bit computational co-processor  SPI, DDRII, RS232, RapidIO

SLIDE 9

9

Multiport switch SpaceWire with embedded processor 1907VM056



Frequency – 100 МHz

SLIDE 10

10 10

1907VM066



SOI «Мicron»



Rad-hard 32-bit microprocessor with coprocessor proccesing and compare data image for navigation and on-board systems

 UСС, В

3,3

 Frequency, МHz

> 100

 Power consumption

@100МHz, W < 6

 Case CPGA 407 pins

Interrupt controller CPU Switch SpaceWire 4 pcs. Arbiter HUB Arbiter PCI controller Memory controller Serial RapidIO Controller 4 pcs. SRAM UART 2 pcs Timers 3 pcs I2C EJTAG SPI GPIO 1533B ALU Register file Correlation

SLIDE 11

1907VK016

 Fault-tolerant microcontroller with TMR

11 11

Interrupt controller CPU TMR Switch SpaceWire 4 pcs. Arbiter HUB Arbiter Memory controller SRAM 128 KB UART 2 pcs Timers 3 pcs SPI 2 pcs. GPIO 32 pcs. 1533B 2 pcs. ALU Register file

SLIDE 12

12 12

9011VА016

 Processor 100 МГц  SRAM 2 МB with correction  FPGA 50 000 gates

CPU

ОЗУ/ППЗУ ОЗУ/ППЗУ CS[3:0] BE[3:0] OE[3:0] WE[4:0] ADR[26:0] < > DATA[39:0] ACK SpaceWire RS-232 CAN JTAG Интерфейс ГОСТ Р 52070 Разовые команды SPI Служебные Служебные Системные Интерфейс ГОСТ Р 52070 JTAG CAN RS-232 SpaceWire FPGA Пользовательские выводы < > IO[182:0] CLOK[1:0] JTAG Системные JTAG INPUT[3:0] Пользовательские выводы Системные

1907ВМ056

D[39:0] A[26:0] CS[3:0] OE[3:0] WE[4:0] BE[3:0] D[31:24] A[18:0] VSUB4 CS1 OE1 WE3 D[23:16] A[18:0] VSUB3 CS1 OE1 WE2 D[15:8] A[18:0] VSUB2 CS1 OE1 WE1 D[7:0] A[18:0] VSUB1 CS1 OE1 WE0 FOF

5576ХС8Т 1667РА014

SRA M

CE# OE# A[18:0] VSUB < > D[7:0] WE# FOF VSUB5 D[39:32] A[18:0] CS1 OE1 WE4

1667РА014

SRA M

CE# OE# A[18:0] VSUB < > D[7:0] WE# FOF

1667РА014

SRA M

CE# OE# A[18:0] VSUB < > D[7:0] WE# FOF

1667РА014

SRA M

CE# OE# A[18:0] VSUB < > D[7:0] WE# FOF

1667РА014

SRA M

CE# OE# A[18:0] VSUB < > D[7:0] WE# FOF

SLIDE 13

Developing boards

 Central processor unit for SSNI “GAMMA-400” based on 1907VM038  Control unit for SSNI “GAMMA-400” based on 1907VM044  Switch Serial RapidIO based on 1907KX018 for OpenVPX systems  Switch SpaceWire based on 1907VM056 for OpenVPX systems  Central processor unit based on 1907VM028 for OpenVPX systems  Central processor unit based on 1907ВМ066 in form factor PC-104  Peripherial module with interface 1533B in form factor PC-104  Performance central processor board :

 Based on 1907ВМ028 – 0,1 Gops на 64-bit operand  Based on 1907ВМ038 – up to 2 GFlops на 32-bit operand

 Performance computer up to 2-8 GFlops on 32-bit operand  Throughput interprocessor channels:

 Up to 6 channels Seraial RapidIO, 1 Gbit/s; up to 6 channels SPACEWIRE,

200 Mbit/s;

13 13

SLIDE 14

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