Practical Enclave Malware with Intel SGX Michael Schwarz, Samuel - - PowerPoint PPT Presentation

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Practical Enclave Malware with Intel SGX Michael Schwarz, Samuel Weiser, Daniel Gruss June 20, 2019 - DIMVA19 Graz University of Technology www.tugraz.at Outline SGX 2 Michael Schwarz , Samuel Weiser, Daniel Gruss Graz University of

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SLIDE 1

Practical Enclave Malware with Intel SGX

Michael Schwarz, Samuel Weiser, Daniel Gruss June 20, 2019 - DIMVA’19 Graz University of Technology
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SLIDE 2

Outline

www.tugraz.at

SGX

2 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 3

Outline

www.tugraz.at

SGX

2 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 4

Outline

www.tugraz.at

SGX

2 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 5

Outline

www.tugraz.at 2 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 6

SGX

www.tugraz.at Application Untrusted part Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 7

SGX

www.tugraz.at Application Untrusted part Create Enclave Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 8

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Trusted Fnc. Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 9

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. Trusted Fnc. Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 10

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. Trusted Fnc. Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 11

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. Trusted Fnc. Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 12

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. Trusted Fnc. Return Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 13

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. Trusted Fnc. Return Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 14

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. . . . Trusted Fnc. Return Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 15

SGX

www.tugraz.at Application Trusted part Call Gate Untrusted part Create Enclave Call Trusted Fnc. . . . Trusted Fnc. Return Operating System 3 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 16

What if?

www.tugraz.at
  • Enclaves are black boxes
4 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 17

What if?

www.tugraz.at
  • Enclaves are black boxes
  • Protected from all applications and OS
4 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 18

What if?

www.tugraz.at
  • Enclaves are black boxes
  • Protected from all applications and OS
  • What if they contain malicious code?
4 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 19

What if?

www.tugraz.at
  • Enclaves are black boxes
  • Protected from all applications and OS
  • What if they contain malicious code?
  • Can we hide zero days?
4 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 20

Threat Model

www.tugraz.at

Intel’s Statement

[...] Intel is aware of this research which is based upon assumptions that are outside the threat model for Intel SGX. The value of Intel SGX is to execute code in a protected enclave; however, Intel SGX does not guarantee that the code executed in the enclave is from a trusted source [...]

5 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 21

SGX Limitations

www.tugraz.at

Classical exploits cannot be mounted within SGX:

6 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 22

SGX Limitations

www.tugraz.at

Classical exploits cannot be mounted within SGX:

  • No syscalls
6 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 23

SGX Limitations

www.tugraz.at

Classical exploits cannot be mounted within SGX:

  • No syscalls
  • No shared memory/libraries
6 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 24

SGX Limitations

www.tugraz.at

Classical exploits cannot be mounted within SGX:

  • No syscalls
  • No shared memory/libraries
  • No interprocess communication
6 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 25

SGX Limitations

www.tugraz.at

Classical exploits cannot be mounted within SGX:

  • No syscalls
  • No shared memory/libraries
  • No interprocess communication
  • Blocked instructions
6 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 26

State-of-the-art Malicious Enclaves

www.tugraz.at
  • Side-channel attacks from SGX [Sch+17]
7 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 27

State-of-the-art Malicious Enclaves

www.tugraz.at
  • Side-channel attacks from SGX [Sch+17]
  • Fault attacks from SGX [Gru+18; Jan+17]
7 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 28

State-of-the-art Malicious Enclaves

www.tugraz.at
  • Side-channel attacks from SGX [Sch+17]
  • Fault attacks from SGX [Gru+18; Jan+17]
  • No real exploits from SGX so far
7 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 29

TEE-REX

www.tugraz.at

TEE-REX

rusted xecution nvironment eturn-oriented-programming ploit

T E E R EX

8 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 30

Attack Overview

www.tugraz.at

Enclave Code Data Stack

9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 31

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP)

9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 32

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP) Write Primitive

Cave

(CLAW)

9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 33

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP) Write Primitive

Cave

(CLAW) ROP injection

chain 9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 34

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP) Write Primitive

Cave

(CLAW) ROP injection

chain 9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 35

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP) Write Primitive

Cave

(CLAW) ROP injection

chain execute 9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 36

Attack Overview

www.tugraz.at

Enclave Code Data Stack Read Primitive

Gadget

(TAP) Write Primitive

Cave

(CLAW) ROP injection

chain execute 9 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 37

Problems

www.tugraz.at
  • Enclave can access host memory...
10 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 38

Problems

www.tugraz.at
  • Enclave can access host memory...
  • ...but crashes on invalid access
10 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 39

Problems

www.tugraz.at
  • Enclave can access host memory...
  • ...but crashes on invalid access
  • No syscall or exception handler available
10 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 40

Transactional Memory

www.tugraz.at
  • Intel TSX: hardware transactional memory
11 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 41

Transactional Memory

www.tugraz.at
  • Intel TSX: hardware transactional memory
  • Multiple reads and writes are atomic
11 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 42

Transactional Memory

www.tugraz.at
  • Intel TSX: hardware transactional memory
  • Multiple reads and writes are atomic
  • Operations in a transaction
11 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 43

Transactional Memory

www.tugraz.at
  • Intel TSX: hardware transactional memory
  • Multiple reads and writes are atomic
  • Operations in a transaction
  • Conflict → abort and roll back
11 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 44

Transactional Memory

www.tugraz.at
  • Intel TSX: hardware transactional memory
  • Multiple reads and writes are atomic
  • Operations in a transaction
  • Conflict → abort and roll back
  • Faults are suppressed
11 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 45

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache 12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 46

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache xbegin xend else path
  • f xbegin
12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 47

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache mov xbegin mov xend else path
  • f xbegin
read read data read set 12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 48

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache mov mov xbegin mov mov xend else path
  • f xbegin
data read read data read data write read set 12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 49

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache mov mov mov xbegin mov mov mov xend else path
  • f xbegin
data read read data read data write read write read set 12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 50

Transactional Memory

www.tugraz.at Thread 1 Thread 0 Cache mov mov mov xbegin mov mov mov xend else path
  • f xbegin
data read read data read data write read write transactional abort read set 12 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 51

TAP

www.tugraz.at
  • Segmentation fault is a fault
13 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 52

TAP

www.tugraz.at
  • Segmentation fault is a fault
  • Suppressed in TSX transaction
13 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 53

TAP

www.tugraz.at
  • Segmentation fault is a fault
  • Suppressed in TSX transaction
  • Abort code → “don’t try again”
13 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 54

TAP

www.tugraz.at
  • Segmentation fault is a fault
  • Suppressed in TSX transaction
  • Abort code → “don’t try again”
  • Valid page → transaction succeeds
13 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 55

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 56

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 57

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 58

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 59

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 60

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 61

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 62

TAP

www.tugraz.at Valid Valid Valid Invalid Invalid Valid Invalid Invalid

Host Memory

14 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 63

TAP

www.tugraz.at
  • Entire memory: 45 min
15 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 64

TAP

www.tugraz.at
  • Entire memory: 45 min
  • Start from saved RIP/RSP: few seconds
15 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 65

TAP

www.tugraz.at
  • Entire memory: 45 min
  • Start from saved RIP/RSP: few seconds
  • Undetectable by OS
15 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 66

TAP

www.tugraz.at
  • Entire memory: 45 min
  • Start from saved RIP/RSP: few seconds
  • Undetectable by OS
  • Used to find ROP gadgets
15 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 67

CLAW

www.tugraz.at
  • Write to mapped page...
16 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 68

CLAW

www.tugraz.at
  • Write to mapped page...
  • ...abort immediately
16 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 69

CLAW

www.tugraz.at
  • Write to mapped page...
  • ...abort immediately

→ No architectural write

16 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 70

CLAW

www.tugraz.at
  • Write to mapped page...
  • ...abort immediately

→ No architectural write

  • Abort code → explicit or implicit
16 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 71

CLAW

www.tugraz.at

Host Memory

R/O R/O R/O N/A N/A R/W N/A N/A

X

17 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 72

CLAW

www.tugraz.at

Host Memory

R/O R/O R/O N/A N/A R/W N/A N/A

X

17 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 73

CLAW

www.tugraz.at

Host Memory

R/O R/O R/O N/A N/A R/W N/A N/A

X

17 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 74

CLAW

www.tugraz.at

Host Memory

R/O R/O R/O N/A N/A R/W N/A N/A

X

17 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 75

TAP+CLAW

www.tugraz.at
  • TAP+CLAW → find writable memory
18 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 76

TAP+CLAW

www.tugraz.at
  • TAP+CLAW → find writable memory

→ Robust write-anything-anywhere primitive

18 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 77

TAP+CLAW

www.tugraz.at
  • TAP+CLAW → find writable memory

→ Robust write-anything-anywhere primitive → Store malicious payload

18 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 78

SGX ROP

www.tugraz.at
  • 1. TAP: find ROP gadgets
19 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 79

SGX ROP

www.tugraz.at
  • 1. TAP: find ROP gadgets
  • 2. CLAW: find writable memory (data cave)
19 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 80

SGX ROP

www.tugraz.at
  • 1. TAP: find ROP gadgets
  • 2. CLAW: find writable memory (data cave)
  • 3. Inject ROP gadgets into host stack
19 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 81

SGX ROP

www.tugraz.at
  • 1. TAP: find ROP gadgets
  • 2. CLAW: find writable memory (data cave)
  • 3. Inject ROP gadgets into host stack
  • 4. Profit!
19 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 82

SGX ROP

www.tugraz.at

Stack

... ... Original saved RIP Original saved RBP Saved RIP Saved RBP Saved RIP Saved RBP leave; ret

20 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 83

SGX ROP

www.tugraz.at

Stack

... ... Original saved RIP Original saved RBP Saved RIP Saved RBP Saved RIP Saved RBP

Fake stack frame

leave; ret

20 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 84

SGX ROP

www.tugraz.at

Stack

... ... Original saved RIP Original saved RBP Saved RIP Saved RBP Saved RIP Saved RBP

Fake stack frame

ROP Chain leave; ret

20 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 85

SGX ROP

www.tugraz.at

Stack

... ... Original saved RIP Original saved RBP Saved RIP Saved RBP Saved RIP Saved RBP

Fake stack frame

ROP Chain

Original saved RIP Original saved RBP

leave; ret

20 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 86

SGX ROP

www.tugraz.at

Stack

... ... Injected RIP Injected RBP Saved RIP Saved RBP Saved RIP Saved RBP

Fake stack frame

ROP Chain

Original saved RIP Original saved RBP

leave; ret

20 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 87

Gadgets

www.tugraz.at

64.8 MB writable data mprotect ROP gadgets SGX Several pages writable data mprotect ROP gadgets

21 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 88

Full Exploit

www.tugraz.at
  • Remote attestation + dynamic loading → no emulation, no

binary

22 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 89

Full Exploit

www.tugraz.at
  • Remote attestation + dynamic loading → no emulation, no

binary

  • Host continues normally → (nearly) no traces
22 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 90

Full Exploit

www.tugraz.at
  • Remote attestation + dynamic loading → no emulation, no

binary

  • Host continues normally → (nearly) no traces
  • Trigger-based → plausible deniability
22 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 91

Full Exploit

www.tugraz.at
  • Remote attestation + dynamic loading → no emulation, no

binary

  • Host continues normally → (nearly) no traces
  • Trigger-based → plausible deniability

→ Securely and stealthily deploying zero days

22 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 92

Try It!

www.tugraz.at

https://github.com/IAIK/SGXROP

23 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 93

Design Problems

www.tugraz.at
  • Asymmetric threat model
24 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 94

Design Problems

www.tugraz.at
  • Asymmetric threat model
  • Enclaves assumed always benign
24 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 95

Design Problems

www.tugraz.at
  • Asymmetric threat model
  • Enclaves assumed always benign
  • Not realistic in most scenarios
24 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
slide-96
SLIDE 96

Design Problems

www.tugraz.at
  • Asymmetric threat model
  • Enclaves assumed always benign
  • Not realistic in most scenarios
  • Full memory access avoidable → reduce attack surface
24 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 97

Takeaways

www.tugraz.at

Takeaways

  • Asymmetric threat model in SGX fosters malware
  • SGX hides and protects malware
  • Easy to port existing malware to SGX ROP
25 Michael Schwarz, Samuel Weiser, Daniel Gruss — Graz University of Technology
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SLIDE 98

Thank you!

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SLIDE 99

Practical Enclave Malware with Intel SGX

Michael Schwarz (@misc0110), Samuel Weiser, Daniel Gruss June 20, 2019 - DIMVA’19 Graz University of Technology
slide-100
SLIDE 100
  • D. Gruss, M. Lipp, M. Schwarz, D. Genkin, J. Juffinger, S. O’Connell, W. Schoechl,
and Y. Yarom. Another Flip in the Wall of Rowhammer Defenses. In: S&P. 2018.
  • Y. Jang, J. Lee, S. Lee, and T. Kim. SGX-Bomb: Locking Down the Processor via
Rowhammer Attack. In: SysTEX. 2017.
  • M. Schwarz, D. Gruss, S. Weiser, C. Maurice, and S. Mangard. Malware Guard
Extension: Using SGX to Conceal Cache Attacks. In: DIMVA. 2017. 27 Michael Schwarz (@misc0110), Samuel Weiser, Daniel Gruss — Graz University of Technology