POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, - - PowerPoint PPT Presentation

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POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, - - PowerPoint PPT Presentation

Oct 20, 2022 322 likes •1.01k views

POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan On-Chip Network Selection 2 Talk Outline Network-on-chip

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SLIDE 1

POLYMORPHIC ON-CHIP NETWORKS

Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan

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SLIDE 2

On-Chip Network Selection

2

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SLIDE 3

Talk Outline

3

  • Network-on-chip Design Space Exploration
  • Networks
  • Workloads
  • Results
  • Polymorphic On-Chip Networks
  • Fabric design
  • Configuring the network
  • Selecting a fabric
  • Evaluation of flexibility
  • Conclusions
  • Future Directions
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SLIDE 4

On-Chip Network Design Space

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{ }

16 nodes 64 nodes 256 nodes 1024 nodes

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SLIDE 5

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x

} {

mesh ring fat-tree butterfly flattened- butterfly

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SLIDE 6

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x

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SLIDE 7

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x

{ }

store-and-forward wormhole

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SLIDE 8

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x

{ }

32 bits 64 bits 128 bits

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SLIDE 9

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x

{ }

4 entries 16 entries 64 entries

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SLIDE 10

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x { 4 entries, 16 entries, 64 entries } = 360 on-chip networks

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SLIDE 11

On-Chip Network Design Space

4

{ 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x { 4 entries, 16 entries, 64 entries } = 360 on-chip networks

cycle-level software simulator

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SLIDE 12

Network Traffic Patterns

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{ }

(injection rate = 1 packet / cycle)

Uniform Random Random Permutation Nearest Neighbor

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SLIDE 13

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Network Measurements: Random Permutation

(Random Permutation)

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SLIDE 14

6

throughput-sensitive application

Network Measurements: Random Permutation

(Random Permutation)

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SLIDE 15

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throughput-sensitive application latency-sensitive application

Network Measurements: Random Permutation

(Random Permutation)

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SLIDE 16

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Network Measurements

(Random Permutation) (Uniform Random) (Nearest Neighbor)

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SLIDE 17

Talk Outline

8

  • Network-on-chip Design Space Exploration
  • Networks
  • Workloads
  • Results
  • Polymorphic On-Chip Networks
  • Fabric design
  • Configuring the network
  • Selecting a fabric
  • Evaluation of flexibility
  • Conclusions
  • Future Directions
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SLIDE 18

The Intuition...

9

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SLIDE 19

The Intuition...

9

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SLIDE 20

The Intuition...

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mesh

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SLIDE 21

The Intuition...

9

mesh

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SLIDE 22

The Intuition...

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mesh

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SLIDE 23

The Intuition...

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ring mesh

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SLIDE 24

The Intuition...

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ring mesh fat tree

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SLIDE 25

Polymorphic On-Chip Network

What it is

  • Sea of structures all networks have in

common

  • Configurable connections between

structures

How it is used

  • Gather structures to arbitrary-degree

switches

  • Connect switches input and output ports

10

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SLIDE 26
  • Network-on-chip Design Space Exploration
  • Networks
  • Workloads
  • Results
  • Polymorphic On-Chip Networks
  • Fabric design
  • Configuring the network
  • Selecting a fabric
  • Evaluation of flexibility
  • Conclusions
  • Future Directions

Talk Outline

11

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SLIDE 27

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1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity

Configuring the Network

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SLIDE 28

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1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity

configurable topology

Configuring the Network

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SLIDE 29

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1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity

configurable topology configurable resource allocation

Configuring the Network

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SLIDE 30

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1.Switch degree

Network Configuration: Switch Degree

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SLIDE 31

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1.Switch degree

Network Configuration: Switch Degree

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SLIDE 32

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1.Switch degree

Network Configuration: Switch Degree

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SLIDE 33

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1.Switch degree

Network Configuration: Switch Degree

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Internal Configuration of a Switch

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Internal Configuration of a Switch

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SLIDE 36

Internal Configuration of a Switch

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SLIDE 37

Internal Configuration of a Switch

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Internal Configuration of a Switch

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SLIDE 39

Internal Configuration of a Switch

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Internal Configuration of a Switch

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Internal Configuration of a Switch

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1.Switch degree 2.Inter-switch connections

Network Configuration: Links

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SLIDE 43

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1.Switch degree 2.Inter-switch connections 3.Packet width

Network Configuration: Packet Width

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SLIDE 44

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1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity

Network Configuration: Queue Capacity

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SLIDE 45

An Example: Configuration of a Mesh

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An Example: Configuration of a Mesh

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An Example: Configuration of a Mesh

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An Example: Configuration of a Mesh

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SLIDE 49

An Example: Configuration of a Mesh

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SLIDE 50

An Example: Configuration of a Mesh

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SLIDE 51

Talk Outline

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  • Network-on-chip Design Space Exploration
  • Networks
  • Workloads
  • Results
  • Polymorphic On-Chip Networks
  • Fabric design
  • Configuring the network
  • Selecting a fabric
  • Evaluation of flexibility
  • Conclusions
  • Future Directions
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SLIDE 52

Polymorphic Fabric Parameter Space

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queue width and depth resources per cluster

  • no. vertical

routing wires

  • no. horizontal

routing resources

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SLIDE 53

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W = {32, 64, 128} D = {4, 16, 64} N = {2, 4, 8, 16} H = {N, 2N} V = {N, 2N}

Polymorphic Fabric Parameter Space

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Polymorphic Fabric Area Overhead

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ASIC implementation Polymorphic implementation

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Polymorphic Fabric Area Overhead

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Area as ASIC

ASIC implementation Polymorphic implementation

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SLIDE 56

Polymorphic Fabric Area Overhead

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Area as ASIC Area in Polymorphic Fabric

ASIC implementation Polymorphic implementation

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SLIDE 57

Polymorphic Fabric Area Overhead

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Area as ASIC Area in Polymorphic Fabric Area Overhead =

ASIC implementation Polymorphic implementation

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SLIDE 58

Polymorphic Fabric Area Overhead

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Area as ASIC Area in Polymorphic Fabric Area Overhead =

ASIC implementation Polymorphic implementation

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SLIDE 59

Polymorphic Fabric Area Overhead

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Area as ASIC Area in Polymorphic Fabric Area Overhead =

ASIC implementation Polymorphic implementation

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SLIDE 60

Area Overhead of Polymorphic Fabrics

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144 polymorphic fabrics Area efficient networks have small queues and generous routing resources

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SLIDE 61

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W={32, 64, 128} D = {4, 16, 64} N = {2, 4, 8, 16} H = {N, 2N} V = {N, 2N}

Polymorphic Fabric Parameter Space

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SLIDE 62

Talk Outline

25

  • Network-on-chip Design Space Exploration
  • Networks
  • Workloads
  • Results
  • Polymorphic On-Chip Networks
  • Fabric design
  • Configuring the network
  • Selecting a fabric
  • Evaluation of flexibility
  • Conclusions
  • Future Directions
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SLIDE 63

Network Selection Under Area Budget

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Of networks smaller than 22 mm , 26 are pareto optimal.

2

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SLIDE 64

Network Selection Under Area Budget

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24 of the 26 optimal networks will fit in 22 mm of polymorphic fabric.

2

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SLIDE 65

Network Selection Under Area Budget

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Polymorphic coverage is strong for all but the tightest area budgets.

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SLIDE 66

Conclusion

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Widely varying on-chip communication patterns can take advantage of a flexible on-chip network. Polymorphic fabric is a coarse grained reconfigurable circuit designed to implement packet-switched networks on chip. Subject to area budget, polymorphic fabric usually offers broad choice of network. Should build polymorphic network unless

  • 1. Area budget highly constrained
  • 2. Application and/or traffic not expected to vary
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Some Future Directions

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  • 1. Hardware implementation
  • 2. Uses beyond application performance

(e.g., on-chip isolation)

  • 3. Incorporation of advanced on-chip network innovations
  • 4. Reconfiguration policy
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SLIDE 68

THANK YOU