Platform-Based Co-Design and Co-Development: Experience, - - PDF document

▶
platform based co design and co development experience
SMART_READER_LITE
LIVE PREVIEW

Platform-Based Co-Design and Co-Development: Experience, - - PDF document

Sep 15, 2022 357 likes •522 views

Platform-Based Co-Design and Co-Development: Experience, Methodology and Trends Grant Martin and Jean-Yves Brunel Cadence Berkeley and Paris Electronic Design Processes Workshop, Monterey, April 21-23, 2002 1 CADENCE DESIGN SYSTEMS, INC.

slide-1
SLIDE 1

1

1 CADENCE DESIGN SYSTEMS, INC.

Platform-Based Co-Design and Co-Development: Experience, Methodology and Trends

Grant Martin and Jean-Yves Brunel Cadence Berkeley and Paris Electronic Design Processes Workshop, Monterey, April 21-23, 2002

2

Outline

  • Design Flows
  • Automotive ‘Software-Software’ codesign
  • Multimedia Design Space Exploration
  • Conclusions
slide-2
SLIDE 2

2

3

Embedded System Development

Application Modelling Application Modelling Architecture Modelling Architecture Modelling Design Space Exploration Design Space Exploration Links to Implementation Links to Implementation Co-Verification Co-Verification

Emphasised in Platform Development Emphasised in Derivative Design

Distributed Automotive Applications over networks – “Software-Software Codesign”

  • Electronic Control Units

(ECU’s)

  • Standard buses (TTP,

CAN, FlexRay)

  • Standard Platforms
slide-3
SLIDE 3

3

5

analysis analysis “functional network” system design system design “real world assumption” implementation implementation “automatic target code gen.” production & after sales production & after sales “handling at the garage” specification specification “zero time assumption” integration & calibration integration & calibration “step into a real car”

Current Design Practices

ECU ECU-

  • 1

1 ECU ECU-

  • 2

2 ECU ECU-

  • 3

3

CAN/TTP CAN/TTP-

  • bus

bus

Matlab Matlab ASCET ASCET .c .c .c ... .c .c .c ... Architecture

Architecture

Requirements Requirements

f1 f1 f2 f2 f3 f3 f4 f4

Engine Control Gear-Box Control

Development process

  • Integration is done too late In the car
  • Tools are PER-ECU – conservative, costly, no tradeoffs

6

Virtual Integration Platform for Distributed Automotive Applications

Buses Buses

Matlab

CPUs Buses Operating Systems Specification

ASCET

Analysis After Sales Service Calibration Implementation

ASCET

Software Components Architectural Models C-Code

IP’s

C++ Development Process Evaluation of Architectural and Partitioning Alternatives

V C C V C C

System Behavior System Architecture

Mapping Performance Simulation

Refinement

f2 f2 f1 f1 f3 f3

slide-4
SLIDE 4

4

7

Scenarios for SW-driven co-development f f ?? f f f f f f f f f f ??

f f f f f f f f f f

?? f f f f f

8

ProjectA HWIntrpt1 HWIntrpt2 Message1 Message2 Message3 Message4

These are behavioral memories The test-bench can include Matlab imported models as well as VCC authored models This is the ASCET imported Project

TestBench HW_Intrpt1 HW_Intrpt2

Module0 SW_Interrupt1 HW_Interrupt1 SW_Interrupt2 Module1 SW_Interrupt HW_Interrupt Module2 SW_Interrupt1 SW_Interrupt2 HWIntrpt1 HWIntrpt2 Timer10msec Timer20ms Timer30ms These are behavioral timers These are the processes for the protected variables These are the modules

  • f the ASCET project

GlobalVariable GlobalVariable2 These are behavioral memories HWIntrpt ReceiveSendTask1 HWIntrpt ReceiveSendTas SWIntrpt ReceiveSendTask3 SWIntrpt ReceiveSendTask4 ReceiveSendTask5 ReceiveSendTask6 ReceiveSendTask7 Module0 SW_Interrupt1 HW_Interrupt1 SW_Interrupt2 Module1 SW_Interrupt HW_Interrupt Module2 SW_Interrupt1 SW_Interrupt2 HWIntrpt1 HWIntrpt2 Timer10msec Timer20ms Timer30ms These are behavioral timers These are the processes for the protected variables These are the modules

  • f the ASCET project

GlobalVariable GlobalVariable2 These are behavioral memories HWIntrpt ReceiveSendTask1 HWIntrpt ReceiveSendTas SWIntrpt ReceiveSendTask3 SWIntrpt ReceiveSendTask4 ReceiveSendTask5 ReceiveSendTask6 ReceiveSendTask7

SW_Interrupt HW_Interrupt Process8 Process9 Process10

HWIntrp Interrupt IntrptReceiveTask1 Interrupt IntrptSendTask1

ASCET-SD imported project in VCC

slide-5
SLIDE 5

5

Broadcast Bus

PPC RTOS Bus Controller ECU 1 internal bus

Behavioral Diagram

Module A Behavioral Memory 1 Module B

Peak Load

PPC RTOS Bus Controller ECU 1 internal bus

Mem Mem

Architectural Bus Memory

Universal Communications Model of Bus

10

Example Design Flow (1): Power Window

  • Definition of a behavioral diagram: Import of functional components (software

projects and modules)

Un ifor m Pu lse s Un iform Pu lses Uni fo rm Pul se s Speed RL Steering WheelTorqu e1 TieRodForce2 Steering WheelAngle2 VoltageBatterie1 Speed FL ClampFo rceRL Steering WheelTorqu e2 CurrentBatterie1 Steerin gWheelAngle4 Sp eedRR YawRate CurrentBatterie2 Voltag eAltern ato r ClampForceFR TieRodForce1 BrakeSwitch PedalSensor1 Later alAcceleration VoltageBatterie2 SpeedFR PedalSensor3 Steering WheelAngle3 TieRodForce3 Steerin gWheelAngle1 PedalSensor2 CurrentAlternator ClampFo rceRR ClampForceFL Steering WheelTorqu e3 HandBrakeSwitch RackPosition3 RackPosition4 RackPosition2 RackPosition1 Tr i gger BordnetStimulator BrakeAc tuator Br a keA ct uat
  • r O
ut Tr i ger Brak eActu ator Br akeA ct uat o r O ut Tr i gger Brak eActu ator Br akeA ct uat o r O ut Tr i gger BrakeAc tuator Br a keA ct uat
  • r O
ut Tr i ger Ste erActua tor St eer A ct uat
  • r O
ut Tr i gger SteerAct uator St eer A ct uat
  • r O
ut Tr i ger H andW heel T o r queA ct u at or H andW heel T o r queA ct u at or W ar ni ngLi ght Y el l ow W ar ni ngLi ght Y el l ow War ni ngLi ght Red War ni ngLi ght Red

2 Track Vehicle Model

Tr i gger D r i ve r St ee r D r i ver Br a ke D r i ver G as D r i ver C l ut ch D r i ver G e ar St eer i ngA ct ua t or 1 St eer i ngA ct ua t or 2 Br a keA ct uat
  • r RR
Br a keA ct uat
  • r RL
Br a keA ct uat
  • r FL
Br a keA ct uat
  • r FR
Un iform Pu lses Driver D r i ver St eer Tr i gg er D r i ver Br ake D r i ve r G as D r i ve r Cl ut ch D r i ver G ear

DbW_TopBlock

BTSetUp A quireSigna l A quir e Signal A quir e Signal A quir e Signal Aquire S ig nal A quireSignal A quireSignal A quireSignal A quireSignal A quireSignal A quireSignal A quireSignal A quireSigna l A quireSignal A quireSignal A quireSignal Aquire S ig nal A quireSignal A quireSignal A quireSignal Aquire S ig nal Aquire S ig nal Aquire S ig nal A quireSignal A quireSigna l Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Aquire S ig nal Com put ePow e r M ana gem e nt M ani pul at
  • r
Com put ePow e r M ana gem e nt Com put ePow e r M ana gem e nt M an i pul at o r M an i pul at o r M an i pul at o r M an i pul at o r M a ni pul at
  • r
Diagnosis M an i pul at o r M an i pul at o r M as t er 1S t eer i ngA ngl eO ut TieRodForce1Fil M a st er 1Br ake F R VoltageBatterie1Fil SpeedRLFil RackPosition4Fil Steering WheelTor que2Fil M ast er 1St eer i ngTor qu eO ut SpeedFRFil vel _veh_m ast er _1 Steerin gWheelAngle4Fil PedalSensor2Fil M ast er 1W ar ni ng ClampFo rceRLFil LateralAccelerationFil YawRateFil BrakeSwitchFil SteeringWh eelAngle1Fil CurrentAlternatorFil RackPosition2Fil A l t er nat
  • r D
i a gnosi s Ti m er PedalSensor3Fil TieRodForce2Fil Steerin gWheelAngle3Fil RackPosition3Fil PedalSensor1Fil Bat t er y2D i a gnosi s ClampForceRRFil M ast er 1Br a keRL CurrentBatterie2Fil Steering WheelTor que3Fil ClampFo rceFLFil Steerin gWheelAngle2Fil SpeedFLFil VoltageBatterie2Fil Steering WheelTor que1Fil Bat t er y1D i agnos i s M ast er 1Br a keFL VoltageAltern ator Fil Speed RRFil M ast er 1Br a keRR ClampForceFRFil CurrentBatterie1Fil Hand BrakeSwitchFil RackPosition1Fil TieRodForce3Fil

Base Brake & ABS Base Steering Handwheel Feedback

Br akeO ut F L Br akeO ut R R Br ake O ut FR Br ake O ut R L St eer i ng Wheel Tor queO ut 2 St eer i ng Wheel Tor queO ut 1 St ee r i ngO ut 2 St ee r i ngO ut 1 M as t er 2War ni ng M ast er 2Br a keFR M ast er 2 B r akeRR M as t er 2St eer i ngTor queO ut M ast er 2Br akeRL M ast er 2Br akeFL M a st er 2St ee r i ng A ngl eO ut v el _ve h_m as t er _2

Master Controller

Br ake D i agnosi s St eer i ngD i agnosi s H WFe edbackD i a gnosi s Diagnosis

Master Controller

slide-6
SLIDE 6

6

11

Design Flow (2)

  • Generation of an ideal communication between the functional components

– No delay or error handling considered. – Functional co-verification

12

Design Flow (3)

TTP Channel 2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS TTPController PPC RTOS
  • Creation of an architectural diagram in VCC
slide-7
SLIDE 7

7

13

Design Flow (4)

  • Mapping the software modules onto the ECU

– Either retaining the original per-ecu mapping from ASCET-SD or creating a new one

Uni f
  • r m
Pul s e s U ni f
  • r m
Pul s e s Uni f or m P u l s e s S pee dRL Stee ring W h ee lTorqu e1 TieRod Forc e2 Stee ring W h ee lAngle 2 Volta ge B a tterie 1 Spe e dFL Cla mpFo rce R L Ste ering W h ee lTorqu e2 Curren tB a tte r ie 1 Stee ringWh ee lA n gle 4 Spee dRR YawRate Curren tB a tte r ie 2 V o ltag eAltern ato r Cla mpFo rce FR TieRod Force 1 Bra keS w itc h Pe da lSen s o r 1 La tera lA c ce le r a tion Volta ge B a tterie 2 Sp ee dFR Pe da lSen s o r 3 Stee ring W h ee lAngle 3 TieRod Forc e3 Stee ring W h ee lA n gle 1 Pe da lSen s o r 2 C u rrentAlte rnato r C la mpF
  • rce
RR Clam pFo r c e FL Ste ering W h ee lTorqu e3 Han dBrake Switch Rac kPo s itio n3 Rac kPo s itio n4 Rac kPo s itio n2 Rac kPositio n1 T r i g e r B ordnetStimulator Br akeAct uat or B r a k e A c t u a t
  • r O u
t T r i g g e r Br akeAct uat
  • r
B r a k e A c t u a t o r O u t T r i g g e r Br akeAct uat
  • r
B r a k e A c t u a t o r O u t T r i g g e r Br akeAct uat or B r a k e A c t u a t
  • r O u
t T r i g g e r St e er Act uat or S t e e r A c t u a t o r O u t T r i g g e r St eer A ct uat or S t e e r A c t u a t o r O u t T r i g g e r H a n d Wh e e l T o r q u e A c t u a t
  • r
H a n d Wh e e l T o r q u e A c t u a t
  • r
W a r n i n g L i g h t Y e l l
  • w
W a r n i n g L i g h t Y e l l
  • w
W a r n i n g L i g h t R e d Wa r n i n g L i g h t R e d 2 Track Vehicle Model T r i g g e r D r i v e r S t e e r D r i v e r B r a k e D r i v e r G a s D r i v e r C l u t c h D r i v e r G e a r S t e e r i n g A c t u a t
  • r
1 S t e e r i n g A c t u a t
  • r
2 B r a k e A c t u a t
  • r
R R B r a k e A c t u a t
  • r
R L B r a k e A c t u a t
  • r
F L B r a k e A c t u a t
  • r
F R Uni f
  • r m
Pul s e s Driver D r i v e r S t e e r T r i g g e r D r i v e r B r a k e D r i v e r G a s D r i v e r C l u t c h D r i v e r G e a r DbW_TopBlock BTSetU p A qu i reSi gnal A qui reSi g nal A qui reSi g nal A qui reSi g nal Aqui r eSi gnal Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l A qui reSi gnal Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eSi gnal Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eS i gn a l Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal A qui reSi gnal A q ui reSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal Aqui r eSi gnal C
  • mp
u t e P
  • w e
r Ma n a g e me n t Ma n i p u l a t
  • r
C
  • mp
u t e P
  • w e
r Ma n a g e me n t C
  • mp
u t e P
  • w e
r Ma n a g e me n t Ma n i p u l a t o r Ma n i p u l a t o r Ma n i p u l a t o r Ma n i p u l a t o r Ma n i p u l a t
  • r
Diagnosis Ma n i p u l a t o r Ma n i p u l a t o r Ma s t e r 1 S t e e r i n g A n g l e O u t TieRod Forc e1F il Ma s t e r 1 B r a k e F R Voltage B a tterie 1Fil Spe ed R LFil R a ck Position4 Fil Ste erin gWhee lTorqu e2 Fil Ma s t e r 1 S t e r i n g T
  • r
q u e O u t Spe ed FR Fi l v e l _ v e h _ ma s t e r _ 1 Ste erin gWhee lAngle 4Fil P eda lSe nsor2Fil Ma s t e r 1 Wa r n i n g C la mp Force RLFil Late ralAc ce lera tionF il YawR a teF il B ra ke Sw itc hFil Ste ering W h ee lAngle 1Fil C u rrent A lte rnat
  • rFil
R a ck Position2 Fil A l t e r n a t
  • r D i
a g n
  • s
i s T i me r P eda lSe nsor3Fil Tie R o dForc e2 Fil Ste erin gWhee lAngle 3Fil R a ck Position3 Fil P eda lSe nsor1Fil B a t e r y 2 D i a g n
  • s
i s C la mp Force RR F il Ma s t e r 1 B r a k e R L Curren tB a tterie 2Fil Ste erin gWhee lTorqu e3 Fil Clam pFo r c e FLFil Ste erin gWhee lAngle 2Fil Spee dFLFil Volta ge B a tterie 2Fil Ste erin gWhee lTorqu e1 Fil B a t t e r y 1 D i a g n o s i s Ma s t e r 1 B r a k e F L V o ltag eAlte r n ato r F il Spe ed R RFil Ma s t e r 1 B r a k e R R Cla mpFo rce FRFil Curren tB a tte r i e1Fil H a ndBrak eSwitc hFil Ra ckP
  • sition1
Fil Tie R o dForc e3 Fil Base Brake & ABS Base Steering Handwheel Feedback B r a k e O u t F L B r a k e O u t R R B r a k e O u t F R B r a k e O u t R L S t e r i n g Wh e e l T o r q u e O u t 2 S t e r i n g Wh e e l T o r q u e O u t 1 S t e e r i n g O u t 2 S t e e r i n g O u t 1 Ma s t e r 2 Wa r n i n g Ma s t e r 2 B r a k e F R Ma s t e r 2 B r a k e R R M a s t e r 2 S t e e r i n g T o r q u e O u t Ma s t e r 2 B r a k e R L Ma s t e r 2 B r a k e F L Ma s t e r 2 S t e e r i n g A n g l e O u t v e l _ v e h _ m a s t e r _ 2 Master Controller B r a k e D i a g n o s i s S t e e r i n g D i a g n o s i s H WF e e d b a c k D i a g n o s i s Diagnosis Master Controller Base Brake & ABS one channel BT SetU p B r a k e O u t R L _ c h a n n e l 4 B r a k e O u t R R _ c h a n n e l 2 B r a k e O u t F R _ c h a n n e l 3 B r a k e O u t F L _ c h a n n e l 4 B r a k e O u t R L _ c h a n n e l 3 B r a k e O u t R R _ c h a n n e l 3 B r a k e O u t F R _ c h a n n e l 4 T i me r B r a k e O u t F R _ c h a n n e l 1 B r a k e O u t R R _ c h a n n e l 1 B r a k e O u t F L _ c h a n n e l 2 B r a k e O u t R R _ c h a n n e l 4 B r a k e O u t F R _ c h a n n e l 2 B r a k e O u t F L _ c h a n n e l 1 B r a k e O u t F L _ c h a n n e l 3 B r a k e O u t R L _ c h a n n e l 2 B r a k e O u t R L _ c h a n n e l 1 Base Brake & ABS one channel Base Brake & ABS one channel Base Brake & ABS one channel V
  • t
e B r a k e C o ma n d V o t e B r a k e C
  • ma
n d V o t e B r a k e C o ma n d V o t e B r a k e C
  • ma
n d S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 1 S t e e r i n g A c t u a t o r O u t _ c h a n e l 2 S t e r i n g A c t u a t o r O u t _ c h a n n e l 3 S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 4 V
  • t
e _ C mp _ R a c k _ A c t BTSe t Up T i me r V o t e _ C mp _ R a c k _ A c t Base Steering one channel Base Steering one channel Base Steering one channel Base Steering one channel S t e e r i n g Wh e e l T o r q u e O u t _ c h a n n e l 2 S t e r i n g Wh e e l T o r q u e O u t _ c h a n n e l 3 S t e e r i n g Wh e e l T o r q u e O u t _ c h a n n e l 1 Handwheel Feedback one channel BTSetUp T i me r V o t e H W F e e d b a c k Handwheel Feedback one channel Handwheel Feedback one channel V o t e H W F e e d b a c k D i agnosi sBr a kePedal C o mp u teB ra keC o mman d f o r c e _ c l p _ f l _ A B S _ d e s f o r c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n g
_ a c c _ v e h _ d e s f o r c e _ c l p _ f r _ A B S _ d e s f o r c e _ c l p _ r r _ A B S _ d e s C
  • mp
_ C md _ A B S _ B r A r b i t e r _ B r BTSetUp T i me r Di a gnosi s B r akePedal C
  • mp
u t e B rak eC
  • mman d
f
  • r
c e _ c l p _ f l _ A B S _ d e s f o r c e _ c l p _ r l _ A B S _ d e s f
  • r c
e _ c l p _ r _ b a s e _ d e s f
  • r c
e _ c l p _ f _ b a s e _ d e s l o n g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C o mp _ C md _ A B S _ B r A r b i t e r _ B r BTSetUp T i me r Di agnosi sBr ak ePedal C o mp u teB ra keC o mma n d f o r c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f o r c e _ c l p _ f r _ A B S _ d e s f
  • r c
e _ c l p _ r r _ A B S _ d e s C o mp _ C md _ A B S _ B r A r b i t e r _ B r BT SetUp T i me r C
  • mp
u t e S t e e r i n g C o mm a n d D i ag n
  • si s_ L
ateral _S en s o rs BTSetUp V o ted R a ck Position T i me r V o ted Stee ringWhe e lA n gle C o mp u t e S t e e r i n g C
  • mma
n d D i a g n
  • si
s _L a t era l _ S en so rs BT SetUp Vote dRac kPo s itio n T i me r Vote dSte erin gWhe elAng le D i ag n o si s F ee d b a ck S e n so rs C o m p u t e S t e e r i n g T o r q u e C o m ma n d BTSet Up T i me r Vote dTie RodFo r c e Vote dSte erin gWhe elTo r q ue D i ag n o si s F ee d b a ck S e n so r s C o mp u t e S t e e r i n g T o r q u e C o mm a n d BTSetUp T i me r Vote dTie R o dForc e Vote dSte erin gWhe elTorq ue C
  • mp
u t e S t e e r i n g C o mm a n d D i ag n
  • si s_ L
ateral _S en s o rs BTSetUp V o ted R a ck Position T i me r V o ted Stee ringWhe e lA n gle C
  • mp
u t e S t e e r i n g C o mm a n d D i ag n
  • si s_ L
ateral _S en s o rs BTSetUp V o ted R a ck Position T i me r V o ted Stee ringWhe e lA n gle E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he dul e r Cyc l
  • St
at i c Sc he dul e r Cyc l
  • St
at i c Sc he dul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y S c he dul e r Cyc l
  • St
at i c Sc he dul e r Cyc l
  • St
at i c Sc he dul e r S i m p l e A S I C I n t e r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r
i t y Sc he dul e r Cyc l
  • St at
i c Sc h e dul e r Cyc l
  • St at
i c Sc h e dul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he d ul e r Cyc l o St at i c Sc he d ul e r Cyc l o St at i c Sc he d ul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i or i t y Sc he dul e r C y c l o St at i c Sc he dul e r C y c l o St at i c Sc he dul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he du l e r Cyc l o S t at i c Sc he d ul e r Cyc l o S t at i c Sc he d ul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i or i t y Sc he dul e r C y c l o St at i c Sc h e dul e r C y c l o St at i c Sc h e dul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he du l e r Cyc l o St at i c Sc he d ul e r Cyc l o St at i c Sc he d ul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he dul e r Cyc l
  • St
at i c Sc he dul e r Cyc l
  • St
at i c Sc he dul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he d ul e r Cyc l o St at i c Sc he d ul e r Cyc l o St at i c Sc he d ul e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s St at i c Pr i
  • r i
t y Sc he dul e r Cyc l
  • St
at i c Sc he du l e r Cyc l
  • St
at i c Sc he du l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t D i a g n
  • si s
F eed b ac k S en so rs C o mp u t e S t e e r i n g T o r q u e C o mma n d BTSet Up T i me r V o tedTie RodFo rce V o ted Stee ringWhe e lTorque D i agnosi sBr a kePedal C o mp u teB ra keC o mman d f o r c e _ c l p _ f l _ A B S _ d e s f
  • r c
e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n g _
a c c _ v e h _ d e s f o r c e _ c l p _ f r _ A B S _ d e s f o r c e _ c l p _ r r _ A B S _ d e s C
  • mp
_ C md _ A B S _ B r A r b i t e r _ B r BTSetUp T i me r

14

Design Flow(5)

Hierarchical Scheduler

Single Task Scheduler Single Task Scheduler Single Task Scheduler Parent Scheduler

  • Generation of the CPU scheduling

– Either manually or automatically in case the original scheduling is preserved

slide-8
SLIDE 8

8

15

Design Flow (6)

  • Computation Performance Simulation

– No communication performance estimation – Co-verification of Computational Resource ‘fit’

16

Design Flow(7)

  • Design iterations

– Re-distribution of the functionality and tuning of the scheduling

C h a n n e l 1 C h a n n e l 1 C h a n n e l 2 l h a n n e l 2 C h a n n e l 2 h a n n e l 1 h a n n e l 1 C h a n n e l 2 l l l TTP C hannel 2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 PPC_TTP Channel1 Channel2 TTPController C h a n n e l 2 PPC RTOS TTPController C h a n n e l 2 PPC RTOS TTPController C h a n n e 1 PPC RTOS TTPController C C h a n n e l 1 PPC RTOS TTPController C h a n n e l 1 PPC RTOS TTPController C h a n n e l 2 C PPC RTOS TTPController C h a n n e l 2 C PPC RTOS TTPController C h a n n e l 1 PPC RTOS TTPController C h a n n e 2 C h a n n e l 1 PPC RTOS TTPController C h a n n e l 2 C h a n n e 1 PPC RTOS TTPController C h a n n e l 2 C h a n n e 1 PPC RTOS C h a n n e l 2 U n i f
  • r
m P l U n i f
  • r
m U n i f
  • r m
P u l s e s SpeedRL St eer i ng W hee l Tor que1 Ti eRodFor ce2 St eer i ng W hee l Angl e2 Vol t age B a t t er i e1 Spe edFL Cl a m pFo r ce R L St eer i ng W hee l Tor que2 Cur r ent B a t t er i e1 St ee r i ngW h eel A n gl e4 SpeedRR YawRat e Cur r ent B a t t er i e2 Vol t ag eAl t er n at or Cl a m pFo r ce FR Ti eRodFor ce1 Br a keSwi t ch Pe dal Sens or 1 La t er al A c cel er a t i
  • n
Vol t age B a t t er i e2 S peedFR Pe dal Sens or 3 St eer i ng W hee l Angl e3 Ti eRodFor ce3 St eer i ng W hee l Angl e1 Pe dal Sens or 2 Cur r ent Al t er n at o r Cl a m pF
  • r ce
R R Cl am pFor ceF L St eer i ng W hee l Tor que3 HandBr akeSwi t ch Rac kPos i t i
  • n3
Rac kPos i t i
  • n4
Rac kPos i t i
  • n2
Rac kPos i t i
  • n1
T r i g g e r B or dnet St i m ul at or B r a k e A c t u a t
  • r
B r a k e A c t u a t
  • r
O u t T r i g e r B r a k e A c t u a t
  • r
B r a k e A c t u a t
  • r
O u t B r a k e A c t u a t
  • r
B r a k e A c t u a t
  • r
T r i g e r S t e e r A c t a t
  • r
S t e r A c t u a t
  • r
O u t T r i g g e r S t e e r A c t u a t o r H a n d W h e l T
  • r
q u e A c t u a t
  • r
W a r n i n g L i g h t Y e l l
  • w
W a r n i n g L i g h t Y e l l
  • w
W a r n i n g L i g h t R e d 2 Track Vehicle Model D r i v e r S t e r D r i v e r B r a k e D r i v e r G a s D r i v e r G e a r S t e r i n g A c t u a t
  • r
1 S t e r i n g A c t u a t
  • r
2 B r a k e A c t u a t
  • r
R R B r a k e A c t u a t
  • r
R L B r a k e A c t u a t
  • r
F L U n i f
  • r
m P u l s e s D river T r i g g e r D r i v e r G a s D r i v e r G e a r DbW_To pBlock B T S et U p Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l A q u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l Aq u i r e S i g n a l C
  • m
p u t e P
  • w
e r M a n a g e m e n t M a n i p u l a t
  • r
C
  • m
p u t e P
  • w
e r M a n a g e m e n t C
  • m
p u t e P
  • w
e r M a n a g e m e n t M a n i p u l a t
  • r
M a n i p u l a t
  • r
M a n i p u l a t
  • r
Di agn
  • s i
s M a n i p u l a t
  • r
Ti eRod For ce 1Fi l Vol t ageBa t t er i e1Fi l SpeedRLFi l RackPo s i t i
  • n4Fi l
St er i ngW h eel Tor que 2Fi l SpeedFRFi l v e l _ v e h _ m a s t e r _ 1 St eer i ng W hee l Angl e4Fi l Pe dal Sens o r 2Fi l Cl am pFor c eRLFi l Lat e r al Accel er at i
  • nFi
l YawRat eFi l B r akeSwi t c hFi l St eer i ng W hee l Angl e1Fi l Cur ent Al t er n at or Fi l RackPo s i t i
  • n2Fi l
T i m e r Pe dal Sens o r 3Fi l Ti eRod For ce 2Fi l St eer i ng W hee l Angl e3Fi l RackPo s i t i
  • n3Fi l
Pe dal Sens o r 1Fi l B a t e r y 2 D i a g n
  • s
i s C l am pFor ceRRFi l M a s t e r 1 B r a k e R L Cur ent Bat t er i e2 Fi l St e er i ngW h eel Tor que 3Fi l Cl am pFor c eFLFi l St eer i ng W hee l Angl e2Fi l Sp eedFLFi l Vol t ageBa t t er i e2Fi l St er i ngW h eel Tor que 1Fi l Vol t age Al t er na t or Fi l SpeedRRFi l M a s t e r 1 B r a k e R R Cl am pFor c eFRFi l Cur r ent B a t t er i e1Fi l HandBr akeSwi t chF i l RackPo s i t i o n1Fi l Ti eRod For ce 3Fi l Base Br ake & ABS Base Steering Handwheel Feedback B r a k e O u t F L B r a k e O u t R R B r a k e O u t F R B r a k e O u t R L S t e e r i n g W h e e l T
  • r
q u e O u t 2 S t e e r i n g W h e e l T
  • r
q u e O u t 1 S t e e r i n g O u t 2 M a s t e r 2 B r a k e R M a s t e r 2 B r a k e R L v e l _ v e h _ m a s t e r _ 2 Master Controller H W F e e d b a c k D i a g n
  • s
i s Dia gnosis Master Controller Base Brake & ABS one channel B T Set U p B r a k e O u t R L _ c h a n n e l 4 B r a k e O u t R R _ c h a n n e l 2 B r a k e O u t F R _ c h a n e l 3 B r a k e O u t F L _ c h a n n e l 4 B r a k e O u t R L _ c h a n e l 3 B r a k e O u t R _ c h a n e l 3 B r a k e O u t F R _ c h a n n e l 4 B r a k e O u t F R _ c h a n n e l 1 B r a k e O u t F L _ c h a n n e l 2 B r a k e O u t R _ c h a n n e l 4 B r a k e O u t F R _ c h a n n e l 2 B r a k e O u t F L _ c h a n e l 3 B r a k e O u t R L _ c h a n n e l 2 Base Brake & ABS one channel Base Brake & ABS one channel Base Brake & ABS one chann el V
  • t
e B r a k e C
  • m
a n d V
  • t
e B r a k e C
  • m
a n d V
  • t
e B r a k e C
  • m
a n d S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 1 S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 2 S t e e r i n g A c t u a t
  • r
O u t _ c h a n e l 3 S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 4 V
  • t
e _ C m p _ R a c k _ A c t B T Set U p T i m e r Base S teering
  • ne
channel Base S teering
  • ne
channel Base Steering on e channel Base Steering one channel S t e e r i n g W h e e l T
  • r
q u e O u t _ c h a n n e l 2 S t e e r i n g W h e e l T
  • r
q u e O u t _ c h a n n e l 3 S t e e r i n g W h e l T
  • r
q u e O u t _ c h a n n e l 1 Handwheel Feedback o ne channel B T Set U p T i m e r Handwheel Feedback one channel Handwheel Feedback o ne channel D i a g n
  • s
i s B r a k e P e d a l Co mp u t e Br a k e Co mma n d f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C
  • m
p _ C m d _ A B S _ B r A r b i t e r _ B r B T S et U p T i m e r D i a g n o s i s B r a k e P e d a l Co mp u t e Br a k e Co mma n d f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C
  • m
p _ C m d _ A B S _ B r B T S et U p T i m e r D i a g n o s i s B r a k e P e d a l Co mp u t e B r a k e Co mma n d f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s A r b i t e r _ B r B T Set U p C
  • m
p u t e S t e r i n g C
  • m
m a n d Di a g n
  • s i
s _ L a t e r a l _ S e n s
  • r
s B T Set U p V ot edRac kPos i t i
  • n
Vot edSt e er i ngW heel Angl e Di a g n o s i s _ L a t e r a l _ S e n s o r s B T Set U p Vot e dRackPos i t i on T i m e r Vot edSt eer i ng W hee l Angl e Di a g n o s i s F e e d b a c k S e n s o r s B T S et U p T i m e r Vot e dTi eRod For c e Vot e dSt e er i ngW h eel Tor que Di a g n
  • s i
s F e e d b a c k S e n s
  • r
s B T S et U p T i m e r Vot ed Ti eRod For ce Vot ed St ee r i ngW he el T o r que Di a g n
  • s i
s _ L a t e r a l _ S e n s
  • r
s B T Set U p V ot edRac kPos i t i
  • n
Vot edSt e er i ngW heel Angl e C
  • m
p u t e S t e r i n g C
  • m
m a n d Di a g n
  • s i
s _ L a t e r a l _ S e n s
  • r
s B T Set U p V ot edRac kPos i t i
  • n
T i m e r Vot edSt e er i ngW heel Angl e E C U _ 2 T a s k s _ 1 B u s C h a E C U _ 2 T a s k s _ 1 B u s C h a E C U _ 2 T a s k s _ 1 B u s C h a E C U _ 2 T a s k s _ 1 B u s C h a E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n E C U _ 2 T a s k s _ 1 B u s C h a n C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r
i t y C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U I n t e r u p t B u s D a t a B u s S t a t i c P r i
  • r i
t y C y c l
  • S t
a t i c S c h e d u l e r C y c l
  • S t
a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r
i t y S h d l C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S h d l S i m p l e A S I C I n t e r r u p t B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r i
t y C y c l
  • S t
a t i c S c h e d u l e r C y c l
  • S t
a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r
i t y C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r
i t y C y c l
  • S t
a t i c S c h e d u l e r C y c l
  • S t
a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U D a t a B u s S t a t i c P r i
  • r
i t y S c h e d u l e r C y c l
  • S
t a t i c S h d l C y c l
  • S
t a t i c S c h e d u l e r S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U D a t a B u s S t a t i c P r i
  • r
i t y S c h e d u l e r C y c l
  • S
t a t i c S h d l C y c l
  • S
t a t i c S c h e d u l e r S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U D a t a B u s S t a t i c P r i
  • r i
t y S c h e d u l e r C y c l
  • S t
a t i c S c h e d u l e r C y c l
  • S t
a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U D a t a B u s S t a t i c P r i
  • r i
t y S c h e d u l e r C y c l
  • S t
a t i c S c h e d u l e r C y c l
  • S t
a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t C P U D a t a B u s S t a t i c P r i
  • r
i t y S c h e d u l e r C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S h d l S i m p l e A S I C I n t e r n a l D a t a B u s E x t e r n a l B u s P
  • r
t Di a g n o s i s F e e d b a c k S e n s
  • r s
C
  • m
p u t e S t e e r i n g T
  • r
q u e C
  • m
m a n d B T Set U p Vot edTi eRodFor ce V ot edSt eer i n gW he el Tor que D i a g n o s i s B r a k e P e d a l Co mp u t e B r a k e Co mma n d f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s A r b i t e r _ B r B T Set U p
slide-9
SLIDE 9

9

17

Un i f
  • r
m P u l s e s Un i f
  • r
m P u l s e s Un i f
  • r m
P u l s e s S p eedRL S teeringW heelT orque1 T ieRodF orce2 S teeringW heelAngle2 Volt a geBatt erie1 S pee dF L ClampF orceRL S teeringW heelT orque2 CurrentB a t terie1 S t ee r ing Whe el An gle4 S p eedRR YawRate CurrentB a t terie2 VoltageAlternator ClampF orceF R T ieRod F
  • rce1
BrakeS w itch P edalS en sor1 L at e r a l Acceleration Volt a geBatt erie2 S p eedF R P edalS en sor3 S teeringW heelAngle3 T ieRodF orce3 S t e eri n gWh eelA n gle1 P edalS en sor2 CurrentAlter n ator Cl a mpF
  • rceR
R Cl amp F
  • rce F
L S teeringW heelT orque3 Hand Br a keS witch RackP ositi
  • n3
RackP ositi
  • n4
RackP ositi
  • n2
R a ckP
  • si
tion 1 T r i g e r Bo rd n e tS timu l a to r Br a k e Ac t u a t
  • r
B r a k e A c t u a t
  • r
O u t T r i g g e r Br a k e Ac t u a t o r B r a k e A c t u a t
  • r
O u t T r i g e r Br a k e Ac t u a t o r B r a k e A c t u a t
  • r
O u t T r i g e r Br a k e Ac t u a t
  • r
B r a k e A c t u a t
  • r
O u t T r i g g e r St e r Ac t u a t o r S t e e r A c t u a t
  • r
O u t T r i g e r St e e r Ac t u a t
  • r
S t e e r A c t u a t
  • r
O u t T r i g g e r H a n d W h e e l T o r q u e A c t u a t
  • r
H a n d W h e e l T o r q u e A c t u a t
  • r
W a r n i n g L i g h t Y e l
  • w
W a r n i n g L i g h t R e d W a r n i n g L i g h t R e d 2 Track Vehicle Model T r i g g e r D r i v e r S t e e r D r i v e r B r a k e D r i v e r G a s D r i v e r C l u t c h D r i v e r G e a r B r a k e A c t u a t
  • r
R R B r a k e A c t u a t
  • r
R L B r a k e A c t u a t
  • r
F L B r a k e A c t u a t
  • r
F R Un i f
  • r m
P u l s e s Driver D r i v e r S t e e r T r i g e r D r i v e r G a s D r i v e r C l u t c h D r i v e r G e a r DbW_TopBlock BTSe tUp Aqui r e Si gna l Aqu i r e Si g na l Aqu i r e Si g na l Aqu i r e Si g na l Aqui r e Si gna l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gna l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gna l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gn a l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l A q ui r e Si g na l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l Aqui r e Si gna l C o m p u t e P o w e r M a n a g e m e n t M a n i p u l a t
  • r
C o m p u t e P o w e r M a n a g e m e n t C o m p u t e P o w e r M a n a g e m e n t M a n i p u l a t
  • r
M a n i p u l a t
  • r
M a n i p u l a t
  • r
M a n i p u l a t
  • r
M a n i p u l a t
  • r
Diagnosis M a n i p u l a t
  • r
M a n i p u l a t
  • r
M a s t e r 1 S t e e r i n g A n g l e O u t T ieRod F
  • rce1 F
il M a s t e r 1 B r a k e F R VoltageBatter ie1 F il S peed RL F i l Rack P
  • sition4F il
S teeringW heelT orque2 F il M a s t e r 1 S t e e r i n g T
  • r
q u e O u t S peed F RF il v e l _ v e h _ m a s t e r _ 1 S teeri n gWh eelA n gle4F i l P eda l S ensor2 F il M a s t e r 1 W a r n i n g ClampF
  • rceRL
F i l L ateralAccelerati
  • nF i
l YawRateF il BrakeS w itchF i l S teeringW heelAngle1 F il C u r ren t AlternatorF il Rack P
  • sition2F il
A l t e r n a t
  • r
D i a g n o s i s T i m e r P eda l S ensor3 F il T ieR
  • dF
  • rce2F i
l S teeri n gWh eelA n gle3F i l Rack P
  • sition3F il
P eda l S ensor1 F il B a t t e r y 2 D i a g n o s i s Cl a mpF
  • rceR
RF i l M a s t e r 1 B r a k e R L C u r ren t Batteri e 2F il S teeringW heelT orque3 F il C lamp F
  • rceF L F
il S teeri n gWh eelA n gle2F i l S peedF L F il VoltageBatter ie2 F il S teeringW heelT orque1 F il B a t t e r y 1 D i a g n o s i s M a s t e r 1 B r a k e F L Vo l tag eA lternatorF i l S peed R RF i l M a s t e r 1 B r a k e R R ClampF orceF RF i l CurrentBatt e r ie1 F il HandBrakeS wit ch F il RackP osit ion 1F il T ieR
  • dF
  • rce3F i
l Base B rake & ABS Base Steering Handwheel Feedbac k B r a k e O u t F L B r a k e O u t R R B r a k e O u t F R B r a k e O u t R L S t e r i n g W h e e l T o r q u e O u t 2 S t e r i n g W h e e l T o r q u e O u t 1 S t e r i n g O u t 2 S t e r i n g O u t 1 M a s t e r 2 W a r n i n g M a s t e r 2 B r a k e F R M a s t e r 2 B r a k e R R M a s t e r 2 S t e r i n g T o r q u e O u t M a s t e r 2 B r a k e R L M a s t e r 2 B r a k e F L M a s t e r 2 S t e r i n g A n g l e O u t v e l _ v e h _ m a s t e r _ 2 Master Controller B r a k e D i a g n o s i s S t e r i n g D i a g n o s i s H W F e e d b a c k D i a g n
  • s
i s Diagnosis Master C ontroller Base Brake & ABS one channel BTSe tUp B r a k e O u t R L _ c h a n n e l 4 B r a k e O u t R R _ c h a n e l 2 B r a k e O u t F R _ c h a n n e l 3 B r a k e O u t F L _ c h a n n e l 4 B r a k e O u t R L _ c h a n n e l 3 B r a k e O u t R _ c h a n n e l 3 B r a k e O u t F R _ c h a n n e l 4 T i m e r B r a k e O u t F R _ c h a n n e l 1 B r a k e O u t R R _ c h a n n e l 1 B r a k e O u t F L _ c h a n e l 2 B r a k e O u t R R _ c h a n n e l 4 B r a k e O u t F R _ c h a n e l 2 B r a k e O u t F L _ c h a n n e l 1 B r a k e O u t F L _ c h a n n e l 3 B r a k e O u t R L _ c h a n e l 2 B r a k e O u t R L _ c h a n n e l 1 Base B rake & ABS one channel Base Brake & ABS one channel Base B rake & ABS one channel V o t e B r a k e C o m a n d V o t e B r a k e C o m a n d V
  • t
e B r a k e C
  • m
a n d V o t e B r a k e C o m a n d S t e r i n g A c t u a t
  • r
O u t _ c h a n n e l 1 S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 2 S t e r i n g A c t u a t
  • r
O u t _ c h a n e l 3 S t e e r i n g A c t u a t
  • r
O u t _ c h a n n e l 4 V
  • t
e _ C m p _ R a c k _ A c t BTSe tUp T i m e r V
  • t
e _ C m p _ R a c k _ A c t Base Steering one channel Base Steering one channel Base Steering one channel B ase Steering one channel S t e r i n g W h e e l T o r q u e O u t _ c h a n n e l 2 S t e e r i n g W h e l T
  • r
q u e O u t _ c h a n n e l 3 S t e e r i n g W h e l T o r q u e O u t _ c h a n e l 1 Handwheel Feedback one channel BTSe tUp T i m e r V
  • t
e H W F e e d b a c k Handwheel Fe edback one channel Handwheel Feedback one channel V
  • t
e H W F e e d b a c k D i a g n o s i s B r a k e P e d a l Com put eBr akeCom m and f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n g
_ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C o m p _ C m d _ A B S _ B r A r b i t e r _ B r BTSe tUp T i m e r D i a g n
  • s i
s B r a k e P e d a l Com put eBr akeCom m and f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C o m p _ C m d _ A B S _ B r A r b i t e r _ B r B TSetU p T i m e r D i a g n o s i s B r a k e P e d a l Com pu t eBr akeCom m and f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C o m p _ C m d _ A B S _ B r A r b i t e r _ B r BTSetU p T i m e r C o m p u t e S t e r i n g C o m m a n d Di agnosi s_Lat er al _Sensor s B TSetU p Vo t ed R a ckP
  • sit
ion T i m e r V
  • t
e dS teeringW heelAng l e C o m p u t e S t e r i n g C o m m a n d Di agnosi s_Lat er al _Sensor s B TSetU p V
  • t
e dRackP osit ion T i m e r VotedS teering Whee l Ang l e D i agnosi s Feedback S ensor s C
  • m
p u t e S t e e r i n g T
  • r
q u e C o m m a n d BTSe tUp T i m e r VotedT ieR
  • dF
  • rce
Vo t ed S teeringW heelT
  • rque
Di agnosi s Feedback Sensor s BTSe tUp T i m e r VotedT i eRod F
  • rce
VotedS teeri n gWh eelT
  • rq ue
C o m p u t e S t e r i n g C o m m a n d Di agnosi s_Lat er al _Sensor s B TSetU p Vo t ed R a ckP
  • sit
ion V
  • t
e dS teeringW heelAng l e C o m p u t e S t e r i n g C o m m a n d Di agnosi s_Lat er al _Sensor s B TSetU p Vo t ed R a ckP
  • sit
ion T i m e r V
  • t
e dS teeringW heelAng l e E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P o r t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t E C U _ 2 T a s k s _ 1 B u s C h a n E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s S t a t i c P r i
  • r
i t y S c h e d u l e r C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S c h e d u l e r S i m p l e A S I C I n t e r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r u p t B u s D a t a B u s S t a t i c P r i
  • r i
t y S c h e d u l e r Cy c l
  • S t
a t i c S c h e d u l e r Cy c l
  • S t
a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s S t a t i c P r i
  • r
i t y S c h e d u l e r C y c l
  • S
t a t i c S c h e d u l e r C y c l
  • S
t a t i c S c h e d u l e r S i m p l e A S I C I n t e r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i
  • r
i t y S c h e d u l e r Cy c l
  • S t a
t i c S c h e d u l e r Cy c l
  • S t a
t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P
  • r
t C P U I n t e r u p t B u s D a t a B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r u p t B u s D a t a B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l
  • S t
a t i c S c h e d u l e r Cy c l
  • S t
a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r r u p t B u s D a t a B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t C P U I n t e r u p t B u s D a t a B u s S t a t i c P r i o r i t y S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r Cy c l o S t a t i c S c h e d u l e r S i m p l e A S I C I n t e r r u p t B u s I n t e r n a l D a t a B u s E x t e r n a l B u s E x t e r n a l B u s P o r t D i agnosi s Feedback Sensor s C
  • m
p u t e S t e e r i n g T
  • r
q u e C o m m a n d BT SetU p T i m e r VotedT ieRodF orce Vo t ed S teeringW heelT orque D i a g n o s i s B r a k e P e d a l Com put eBr akeCom m and f
  • r
c e _ c l p _ f l _ A B S _ d e s f
  • r
c e _ c l p _ r _ b a s e _ d e s f
  • r
c e _ c l p _ f _ b a s e _ d e s l
  • n
g _ a c c _ v e h _ d e s f
  • r
c e _ c l p _ f r _ A B S _ d e s f
  • r
c e _ c l p _ r r _ A B S _ d e s C o m p _ C m d _ A B S _ B r A r b i t e r _ B r BTSetU p T i m e r

Design Flow(8)

  • Initialization of the UCM performance model.

– Automated generation of an initial communication matrix that carries the dependency

  • f the functional system mapping.
  • Definition of a specific bus protocol implementation

– UCM parameterization. Definition of the communication cycle layout. Data frame definition.

Bus Type Pattern

18

Design Flow (9)

  • Performance simulation including the bus latencies
  • Full System co-verification: both communications and computation

Design Iterations

Bus Type Pattern

slide-10
SLIDE 10

10

19

vccMap Database

Design Data Exported from VCC diagrams using “VCCAPI”

vccDse Database

Design Space Navigator (SQL queries)

vccSim Database

Performance Data Collected by VCC probes under control

  • f system events

Data Analysis Workbooks for specific roles (Excel+StatBox) Process Analyst

map_FAKIR_Diagrams.MPEG_VIPER_S1 Breakdown of Workload on Architectural Resources of Type: RTOS, CORE, MEM & BUS - Per Process - Average Intrinsic Delay per Frame (sec) 3:ofileproc 4:drop_finfo 5:in_es 6:t_decMV 7:t_memory 8:t_writeMB 9:t_add 10:t_idct 11:t_predict 12:t_vld 13:t_isiq 14:t_output 15:t_memMan 16:t_hdr proc R2c R25c R27c R30c R34b R16m R27m R30m R32m E1s E16s E27s E2c E16c E27c E30c E34b E32m W1s W2c W27c W30c map_FAKIR_Diagrams.MPEG_VIPER_SH2 Frame Processing - Actual Delay (sec) 28P 27B 26B 25P 24B 23B 22I 21B 20B 19P 18B 17B 16P 15B 14B 13P 12B 11B 10I 9B 8B 7P 6B 5B 4P 3B 2B 1I 26P 25B 24P 23P 22B 21I 20I 19B 18P 17P 16B 15P 14P 13B 12P 11P 10B 9I 8I 7B 6P 5P 4B 3P 2P 1B 29B 28P 27B 26B 25P 24B 23B 22I 21B 20B 19P 18B 17B 16P 15B 14B 13P 12B 11B 10I 9B 8B 7P 6B 5B 4P 3B 2B 1I procID 15:t_hdr 14:t_memMan (Peeker) 8:t_output 28 “Peeker” Frames in … 2 sec!

Application Analyst

map_FAKIR_Diagrams.MPEG_VIPER_SH2 YAPI Transactions - Write - Number of bytes per channel per frame 0,00E+00 5,00E+05 1,00E+06 1,50E+06 2,00E+06 2,50E+06 3,00E+06 3,50E+06 4,00E+06 1 3 5 7 9 11 13 15 17 19 21 23 25 nbByte 2 4 7 9 10 11 12 14 16 17 18 19 22 23 25 26 27 30 33 35 36 37

Communication Analyst

Classification

e s co sy_i ni t f i nf o S i n f o Y
  • _I
nf o Y
  • _D
a t a U
  • _I
nf o U
  • _D
a t a V
  • _I
nf o V
  • _D
a t a T vl d _bi t s_I n h d r _ s t a t u s _ O u t Td ecM V _p r op _pr ed_O u t Tdec MV _ pr o p_m v_ O ut co sy_ i n i t T vld Thdr _st at us _I n T h dr Td ecM V _p r op _m v_I n Tde cM V _pr
  • p_
pr e d_I n d e c M V _ p r
  • p
_ s e q _ I n d e c M V _ p r
  • p
_ p i c _ I n Tpr edi ct _m v_O u t T pr e di ct _ pr o p_p r ed _O ut T pr e di ct _ pr o p_s eq_ O ut s y _ i n i t T d ec M V Tpr e di ct _pr
  • p_p
r e d_I n Tpr e di ct _m v_I n Tp r e di c t _ pr o p_s eq_I n Tpr ed i c t _p r op _pi c_I n p r e d i c t _ r e f _ m e m _ i d _ I n Tm e m o r y_ m b_p_ I n Tp r ed i c t _ t ok en_ O ut
  • s
y _ i n i t T pr ed ict m b_Q FS_ I n Ti si q_ pr o p_se q_I n Ti si q_ pr o p_m b_I n m b_F _O ut Ti dct _pr
  • p_
seq _O ut Ti d ct _pr
  • p_m
b _O ut c
  • sy
_i ni t T i si q m b _F_I n Ti dct _p r op _se q_I n Ti dct _p r op _m b_I n m b _f _ O ut Tad d_p r op _se q_O ut Tad d_pr
  • p_
m b_O ut
  • s
y _ i n i t T id ct m b_f _I n Tad d_pr
  • p
_se q_I n Tad d_pr
  • p
_m b_I n m b_d_ O ut Tw r i t e M B _pr
  • p_
seq _O ut Tw r i t eM B _ pr o p_m b_ O ut
  • s
y _ i n i t T ad d m b_d _I n Tw r i t e M B _pr
  • p_
seq _I n Tw r i t eM B _ pr o p_pi c_ I n Tw r i t eM B _ pr o p_m b_ I n Tw r i t e M B _m em _i d_ I n T m e m Ma n_p r op _se q_O ut Tm em M an _cm d_ O u t m e m
  • r
y _ m b _ t
  • k
e n _ O u t Tm em M an _pr
  • p_
pi c _O ut cos y_i ni t T w rite M B Tm em M an_c m d_I n Tm em Ma n_p r op _se q_I n Tw r i t e M B _pi c_ I n Tw r i t e MB _m em _i d_O u t p r e d i c t _ r e f _ m e m _ i d _ O u t Tou t p ut _ cm d_O u t Tou t p ut _ pr o p_s eq_ O ut m e m
  • r
y _ p r
  • p
_ s e q _ O u t T
  • ut
put _pi c_ O ut m e m
  • r
y _ s t a t _ r d y _ O u t c
  • sy
_i ni t T m e m M an m e m M a n _ s t a t _ r d y _ I n Tp r ed i c t _t
  • k
en_ I n w r i t e M B _ t
  • k
e n _ I n Tou t pu t _ l i ne _adr e ss_ I n Tadd _m b_p_ O ut Tou t pu t _ l i ne _da t a _O ut c
  • sy
_i ni t T m e m
  • ry
To ut put _pr
  • p_s
eq _I n Tou t pu t _ cm d_I n Tm e m o r y _l i ne _da t a _I n Tm e m M an _pi c_ I n Y _ I nf
  • Y
_D at a U _ I nf
  • U
_D at a V _ I nf
  • V
_ D at a Si nf
  • f i
nf o Tm e m
  • r y
_l i n e_a ddr ess _O ut c
  • sy
_i ni t T
  • u
tp ut C re a ted by C OS Y ( c) M a y 200 1 YHS1 YSH1 YSH1 YSH1 YSH1 YHS1 VHH1 YSS1 YHH1 YSH1 YHS1 YHH1 YSH1 YSS1 YHHP YHHP YSH1 YHH1 YHHP YHHP YHH1 YHH1 YHH1 YHHP YSH1 YHHP YHHP YHH1 YHHP YHHP YSH1 YSH1 YSH1 YHH1 YSH1 YHS1 YHSP YHSP YHSP YHH1 YHHP YSH1 YSH1 YSH1 YSH1 YSH1 EJ TA G FPB C _ MP I C M_ br i dg e M PB C _G L O B A L B O O T_D B G SM C A R D I C 1_ 2 U A R T1 _3 C LO C K S U SB I EEE13 94 S PD I O A I O 1_ 3 SS I TPB C f _pi _b us m _pi _b us t _ pi _bus C _B r i dge PR 394 V I P1_2 I C P1_2 M B S MSP 1_2 P CI D E FP I M I TPI C G PI O V M PG M M I M e m
  • r
y p SO S R TO S T M _ 3 2 1 8 V MPG _ A U X FR _M EM

Multimedia Applications – Design Space Exploration

20

Export Mapping Data to DataBase

es cos y_init finfo Sinfo Yo_Info Yo_Data Uo_Info Uo_Data Vo_Info Vo_Data T vld_bits_In h d r _ s t a t u s _ O u t TdecMV_prop_pred_Out TdecMV_prop_m v_Out cos y_init

Tvld

T hdr_status_In

Thdr

TdecMV_prop_m v_In T decMV_prop_pred_In d e c M V _ p r
  • p
_ s e q _ I n d e c M V _ p r
  • p
_ p i c _ I n Tpredict_mv_Out Tpredict_prop_pred_Out Tpredict_prop_seq_Out s y _ i n i t

TdecMV

Tpredict_prop_pred_In T predict_m v_In Tpredict_prop_seq_In Tpredict_prop_pic_In p r e d i c t _ r e f _ m e m _ i d _ I n T mem ory_mb_p_In T predict_token_Out s y _ i n i t

Tpredict

mb_QFS_In Tisiq_prop_seq_In Tisiq_prop_mb_In mb_F_Out Tidct_prop_seq_Out Tidct_prop_mb_Out cosy_init

Tisiq

mb_F_In Tidct_prop_seq_In Tidct_prop_mb_In mb_f_Out T add_prop_seq_Out Tadd_prop_m b_Out s y _ i n i t

Tidct

m b_f_In Tadd_prop_seq_In Tadd_prop_mb_In mb_d_Out TwriteMB_prop_s eq_Out T writeMB_prop_mb_Out s y _ i n i t

Tadd

mb_d_In T writeMB_prop_seq_In TwriteMB_prop_pic_In TwriteMB_prop_mb_In TwriteMB_mem_id_In Tm emMan_prop_seq_Out T memMan_cm d_Out m e m
  • r
y _ m b _ t
  • k
e n _ O u t Tm emMan_prop_pic_Out cosy_init

TwriteMB

T memMan_cm d_In TmemMan_prop_seq_In Tw riteMB_pic_In TwriteMB_mem_id_Out p r e d i c t _ r e f _ m e m _ i d _ O u t Toutput_cmd_Out Toutput_prop_seq_Out m e m
  • r
y _ p r
  • p
_ s e q _ O u t Toutput_pic_Out m e m
  • r
y _ s t a t _ r d y _ O u t cos y_init

TmemMan

m e m M a n _ s t a t _ r d y _ I n Tpredict_token_In w r i t e M B _ t
  • k
e n _ I n T output_line_addres s_In Tadd_mb_p_Out T output_line_data_Out cos y_init

Tmemory

Toutput_prop_seq_In Toutput_cm d_In Tm emory_line_data_In T memMan_pic_In Y_Info Y_Data U_Info U_Data V_Info V_Data Sinfo finfo Tm emory_line_address _Out cos y_init

Toutput Created by COSY (c) May 2001

EJTAG FPBC_MPIC M_bridge MPBC_GL OBAL BOOT _DBG SMCARD IIC1_2 UART1_3 CLOCKS USB IEEE1394 SPDIO AIO1_3 SSI T PBC f_pi_bus m_pi_bus t_pi_bus C_Bridge PR3940 VIP1_2 ICP1_2 MBS MSP1_2 PCI DE FPIMI TPIC GPIO VMPG MMI Memor y pSOS RTOS TM_3218 VMPG_ AUX FR_MEM YHS1 YSH1 YSH1 YSH1 YSH1 YHS1 VHH1 YSS1 YHH1 YSH1 YHS1 YHH1 YSH1 YSS1 YHHP YHHP YSH1 YHH1 YHHP YHHP YHH1 YHH1 YHH1 YHHP YSH1 YHHP YHHP YHH1 YHHP YHHP YSH1 YSH1 YSH1 YHH1 YSH1 YHS1 YHSP YHSP YHSP YHH1 YHHP YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1 YSH1
  • ut
cos y_init TBINF ILE_unsig ned_char in cos y_init TDROP_field_inf
  • CA_Info
CA_Data CB_Info CB_Data CC_Info CC_Data sinfob cosy_init TBE es finfo Sinfo Yo_Info Yo_Data Uo_Info Uo_Data Vo_Info Vo_Data cosy_init SMPEGDecode cosy_init beh_MPEG_Proces ses

Created by COSY (c) June 2001

EJTAG FPBC_MPIC M_bridge MPBC_GL OBAL BOOT _DBG SMCARD IIC1_2 UART1_3 CLOCKS USB IEEE1394 SPDIO AIO1_3 SSI T PBC f_pi_bus m_pi_bus t_pi_bus C_Bridge PR3940 VIP1_2 ICP1_2 MBS MSP1_2 PCI DE FPIMI TPIC GPIO VMPG MMI Memor y pSOS RTOS TM_3218 VMPG_ AUX FR_MEM
slide-11
SLIDE 11

11

21

System-Observation-Windows

Frame Port Name Transaction Item Actual Intra ID Nb Nb Delay Delay 1 Tvld_bits_In 324 20,736 0.14 0.02 1 Tvld_cmd_In 208 208 0.13 0.00 1 Tvld_prop_pic_In 1 1 0.00 0.00 1 Tvld_prop_slice_In 36 36 0.00 0.00 1 mb_QFS_Out 1,622 622,704 6.66 0.65 1 Thdr_status_Out 208 208 0.01 0.01 1 Tisiq_prop_mb_Out 1,622 1,622 0.03 0.03 1 TdecMV_prop_mv_Out 1,622 1,622 0.04 0.04 … … … …. … …. 2 Tvld_bits_In 525 33,600 0.23 0.03 2 Tvld_cmd_In 206 206 0.12 0.00 2 Tvld_prop_pic_In 1 1 0.00 0.00 2 Tvld_prop_slice_In 36 36 0.00 0.00 2 mb_QFS_Out 1,619 621,696 6.53 0.65 2 Thdr_status_Out 206 206 0.01 0.01 2 Tisiq_prop_mb_Out 1,619 1,619 0.03 0.03 2 TdecMV_prop_mv_Out 1,619 1,619 0.04 0.04 2 TdecMV_prop_pred_Out 1,619 1,619 0.09 0.09 … … … … … … Frame Requestor Delay Delay ID Mean StDev 1 Behavior/in_es_out_sender 5.64E-06 3.00E-06 1 Behavior/decode/t_vld_Tvld_bits_In_receiver 2.91E-06 1.20E-06 1 Behavior/decode/t_hdr_Tvld_cmd_Out_sender 2.40E-07 1.17E-14 1 Behavior/decode/t_vld_Tvld_cmd_In_receiver 2.40E-07 1.17E-14 1 Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender 2.16E-06 0.00E+00 1 Behavior/decode/t_vld_Tvld_prop_pic_In_receiver 2.16E-06 0.00E+00 1 Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender 7.20E-07 1.22E-14 … …. … … 2 Behavior/in_es_out_sender 5.64E-06 3.00E-06 2 Behavior/decode/t_vld_Tvld_bits_In_receiver 2.91E-06 1.20E-06 2 Behavior/decode/t_hdr_Tvld_cmd_Out_sender 2.40E-07 1.17E-14 2 Behavior/decode/t_vld_Tvld_cmd_In_receiver 2.40E-07 1.17E-14 2 Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender 2.16E-06 0.00E+00 2 Behavior/decode/t_vld_Tvld_prop_pic_In_receiver 2.16E-06 0.00E+00 2 Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender 7.20E-07 1.22E-14 2 Behavior/decode/t_vld_Tvld_prop_slice_In_receiver 7.20E-07 1.22E-14 … … … …

es co sy_ i nit finfo S i nfo Yo_In fo Y
  • _Data
Uo_In fo U
  • _Data
Vo_In fo V
  • _Data
T vld_ bi ts_ In h d r _ s t a t u s _ O u t T d ecM V _ prop _pred _Out T d ecM V _ prop _mv_ Out co sy_ i n i t Tvld T hdr_ stat u s_In Thdr T d ecM V _ prop _mv_ In T d ecMV_p rop_ pred _In d e c M V _ p r
  • p
_ s e q _ I n d e c M V _ p r
  • p
_ p i c _ I n T predict_mv _Out T predict_p rop_ pred _Out T predict_p rop_ seq_ Out
  • s
y _ i n i t TdecMV T pred i c t_pro p_p red_In T pred i c t _ mv_ In T predict_p rop_ seq_ In T p redict_pro p_p i c _In p r e d i c t _ r e f _ m e m _ i d _ I n T m emory_ mb_ p_In T pred i c t _ t
  • ken _Out
  • s
y _ i n i t Tpredict mb _QF S _In T isiq_p rop_ seq_ In T isiq_p rop_ mb_ In mb_F _Ou t T i d ct_p rop_ seq_ Out T idc t _ prop _mb _Out c osy _init Tisiq m b_F _In T idc t _ prop _seq _In T idc t _ prop _mb _In mb_ f _ Out T add _pro p_se q_Ou t T ad d_p rop_ mb_Ou t
  • s
y _ i n i t Tidct mb_ f_In T ad d_p rop_ seq_ In T ad d_p rop_ mb_ In mb_d _Out T writeMB_pro p_se q_Out T writ e MB _ prop _mb _Out
  • s
y _ i n i t Tadd mb_ d_In T wri teM B _p rop_ seq_ In T writeMB_pro p_p i c _In T writeMB_pro p_m b_In T w r iteMB_mem _i d _In T m emMan _pro p_se q_Ou t T mem Man_ cmd_ Out m e m
  • r
y _ m b _ t
  • k
e n _ O u t T memM an_p rop_ pic_Ou t co sy_ i n i t TwriteMB T memMa n_c md_In T memM an_ prop _seq _In T writeMB_pic_In T writ e MB _ mem_ i d_ Out p r e d i c t _ r e f _ m e m _ i d _ O u t T o utput_c md_ Out T
  • utput_ prop _seq _Out
m e m
  • r
y _ p r
  • p
_ s e q _ O u t T
  • utput_ pi
c _Out m e m
  • r
y _ s t a t _ r d y _ O u t c osy _init TmemMan m e m M a n _ s t a t _ r d y _ I n T p redict_tok en_In w r i t e M B _ t
  • k
e n _ I n T
  • utput_ l
ine_ addre ss_In T a dd_ mb_p _Out T o utput_line_d ata_Ou t cos y_init Tmemory T ou t p ut_pro p_s eq_In T
  • utput_ cmd_ In
T memo ry_li n e_d at a _In T memM an_p i c _In Y _ Info Y _ Dat a U _ Info U _ Dat a V _ Info V _ Dat a S i nfo fi n fo T memo ry_li n e_ad dress_ Out cos y_init Toutput Created by COSY (c) May 2001 EJTAG FPBC_MPIC M_bridge MPBC_GL OBAL BOOT _DBG SMCARD IIC1_2 UART1_3 CLOCKS USB IEEE1394 SPDIO AIO1_3 SSI T PBC f_pi_bus m_pi_bus t_pi_bus C_Bridge PR3940 VIP1_2 ICP1_2 MBS MSP1_2 PCI DE FPIMI TPIC GPIO VMPG MMI Memor y pSOS RTOS TM_3218 VMPG_ AUX FR_MEM

Pict 1 Pict 2

For, e.g. Each MPEG Frame Measure… e.g. MEMORY usage e.g. process activity

22

“Probe-Synch” & Observer Probes

Probe-Synch is triggered on conditions in a behavioral block (i.e. MPEG frame decoded) Control up to 200 distributed

  • bserver probes of different

types: i.e Memory probes, Bus probes, CPU “Delay” probes etc… Observer Probes record summary data at the granularity defined by the peeker

BUS OBSERVER PROBE CPU OBSERVER PROBE MEMORY OBSERVER PROBE

slide-12
SLIDE 12

12

23

Calculate Average Actual & Intrinsic Communication Rates of all “YAPI” application level Channels Calculate Average Actual & Intrinsic Communication Rates of all “YAPI” application level Channels

Queries 1: link Map & Simulation data

SELECT simComAppYapi.sessionCounter AS frameID…, simComAppYapi.actualDelay,… FROM mapComAppYapi INNER JOIN fctProc ON mapComAppYapi.srcProcID = fctProc.ID… WHERE simComAppYapi.VccInstanceName)=[fctProc].[diagName] & "/" & [fctProc].[procName];

chanID frameID nbTransaction nbItem nbByte actualDelay intrinsicDelay 2 3 5,76E+02 5,76E+02 6,91E+03 6,06E-04 6,06E-04 2 10 5,10E+01 5,10E+01 6,12E+02 4,56E-05 4,56E-05 16 18 1,62E+03 1,62E+03 4,54E+04 7,26E-02 3,54E-05

Key to retrieve Design “Mapping” Decision Simulation results Simulation “Frame” Context

24

Calculate Average Actual & Intrinsic Communication Rates of all “YAPI” application level Channels Calculate Average Actual & Intrinsic Communication Rates of all “YAPI” application level Channels

Queries 2: calculate basic Statistics

SELECT DISTINCTROW Avg([nbByte]/[actualDelay]) AS AvgOfActualRate, StDev([nbByte]/[actualDelay]) AS StDevOfActualRate,… Avg([nbByte]/[intraDelay]) AS AvgOfIntraRate, … INTO staComAppYapiRate_perChan FROM mkStaComAppYapiRate_perChan_step1 GROUP BY chanID…;

comA ppClas s trans action chanI D portID AvgOfActualRate StDevOf ActualR ate MinOfA ctualR ate MaxOfA ctualRat e AvgOfIntraRate YAPI Rd 2 14 5,61E+06 5,98E+0 4 5,55E+ 06 5,77E+0 6 6,09E+06 YAPI Wr 2 48 7,34E+06 1,58E+0 6 6,47E+ 06 1,21E+0 7 1,13E+07 YAPI Rd 3 15 6,27E+07 6,27E+ 6,27E+0 6,67E+07

slide-13
SLIDE 13

13

25

map_FAKIR_Diagrams.MPEG_VIPER_SH2 Frame Processing - Actual Delay (sec)

28P 27B 26B 25P 24B 23B 22I 21B 20B 19P 18B 17B 16P 15B 14B 13P 12B 11B 10I 9B 8B 7P 6B 5B 4P 3B 2B 1I 26P 25B 24P 23P 22B 21I 20I 19B 18P 17P 16B 15P 14P 13B 12P 11P 10B 9I 8I 7B 6P 5P 4B 3P 2P 1B 29B 28P 27B 26B 25P 24B 23B 22I 21B 20B 19P 18B 17B 16P 15B 14B 13P 12B 11B 10I 9B 8B 7P 6B 5B 4P 3B 2B 1I

0,00 0,20 0,40 0,60 0,80 1,00

tStart procID

15:t_hdr 14:t_memMan (Probe-Synch) 8:t_output 28 Frames in … 2 sec! Application Analyst

26

map_FAKIR_Diagrams.MPEG_VIPER_S1 Breakdown of Process Execution on basic Architectural Resources of Type: CORE, MEM & BUS - Average Actual Delay per Frame (sec)

R2c R2c R2c R2c R2c R2c R2c R2c R2c R2c R2c R2c R2c R25c R27c R27c R30c R30c R30c R30c R34b R34b R34b R34b R34b R34b R34b R34b R34b R34b R34b R34b R34b R16m R27m R27m R27m R30m R32m R32m R32m R32m R32m R32m R32m R32m R32m R32m R32m R32m R32m E2c E2c E2c E2c E2c E2c E2c E2c E2c E16c E27c E27c E27c E30c E30c E30c E30c E34b E34b E34b E34b E34b E34b E34b E34b E34b E32m E32m E32m E32m E32m E32m E32m E32m E32m W2c W2c W2c W2c W2c W2c W2c W2c W2c W2c W2c W27c W27c W27c W30c W30c W30c W30c W34b W34b W34b W34b W34b W34b W34b W34b W34b W34b W34b W34b W6m W6m W6m W25m W27m W30m W30m W30m W32m W32m W32m W32m W32m W32m W32m W32m W32m W32m W32m

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 3,00E-01 3,50E-01 4,00E-01

3:ofileproc 4:drop_finfo 5:in_es 6:t_decMV 7:t_memory 8:t_writeMB 9:t_add 10:t_idct 11:t_predict 12:t_vld 13:t_isiq 14:t_output 15:t_memMan 16:t_hdr

proc

AvgOfactualDelay R2c R25c R27c R30c R34b R16m R27m R30m R32m E2c E16c E27c E30c E34b E32m W2c W27c W30c W34b W6m W25m W27m W30m

Process Analyst Body-Function Exec Delay On Memory “32” IO- (Write Trans.) Execution Delay On CPU “2” Body-Function Execution Delay On CPU “2” IO-(Read Trans.) Exec Delay On CPU “2” Process “t-predict”

slide-14
SLIDE 14

14

27

map_FAKIR_Diagrams.MPEG_VIPER_S1 YAPI Transactions - Write - Number of bytes per channel per frame

0,00E+00 5,00E+05 1,00E+06 1,50E+06 2,00E+06 2,50E+06 3,00E+06 3,50E+06 4,00E+06

1 3 5 7 9 11 13 15 17 19 21 23 25

frameID nbByte

2 4 6 8 9 10 11 14 15 17 18 20 21 22 23 26 30 32 34 35 36 37 40

Communication Analyst

28

map_FAKIR_Diagrams.MPEG_VIPER_SH2 YAPI IO Rates - avg Actual versus avg Intrinsic (Byte/sec, log scale)

75Rd 71Rd 70Rd 66Rd 65Rd 64Rd 62Rd 59Rd 56Rd 54Rd 53Rd 50Rd 48Rd 47Rd 45Rd 44Rd 43Rd 42Rd 40Rd37Rd 36Rd 33Rd 30Rd 27Rd 26Rd 25Rd 23Rd 19Rd 18Rd 17Rd 16Rd 14Rd 12Rd 11Rd 10Rd 9Rd 4Rd 3Rd 2Rd 75Wr 71Wr 70Wr 66Wr 65Wr 64Wr 62Wr 59Wr 56Wr 54Wr 53Wr 50Wr 48Wr 47Wr 46Wr 45Wr 44Wr 43Wr 42Wr 40Wr 37Wr 36Wr 35Wr 33Wr 30Wr 27Wr 26Wr 25Wr 23Wr 22Wr 19Wr 18Wr 17Wr 16Wr 14Wr 12Wr 11Wr 10Wr 9Wr 7Wr 4Wr 2Wr 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04 1,00E+05 1,00E+06 1,00E+07 1,00E+08 1,00E+09 1,00E+10 1,00E+11 1,00E+05 1,00E+06 1,00E+07 1,00E+08 1,00E+09 1,00E+10

AvgOfIntraRate AvgOfActualRate

YAPI.Rd YAPI.Wr

Communication Analyst

Very bad “performance” compared to “intrinsic rate”; Arbitration issue or… always busy waiting for input?

slide-15
SLIDE 15

15

29

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis - YAPI Application Level Communication

itemSize fifoDepth AvgOfnbTransaction AvgOfnbItem AvgOfactualDelay AvgOfPerf

  • 1
  • 0,8
  • 0,6
  • 0,4
  • 0,2

0,2 0,4 0,6 0,8 1

  • 1
  • 0,8
  • 0,6
  • 0,4
  • 0,2

0,2 0,4 0,6 0,8 1

  • - axe F1 (34 %) -->
  • - axe F2 (23 %) -->

Opposed characteristics Linked characteristics

Principal Component Analysis Characteristics

30

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis - YAPI Application Level Communication

10Rd.VHH1 10Wr.VHH1 11Rd.VHH1 11Wr.VHH1 12Rd.VHH1 12Wr.VHH1 14Rd.YSH1 14Wr.YSH1 16Rd.YHHP 16Wr.YHHP 17Rd.YHHP 17Wr.YHHP 18Rd.YSH1 18Wr.YSH1 19Rd.YSH1 19Wr.YSH1 22Wr.YHHP 23Rd.YHS1 23Wr.YHS1 25Rd.YSH1 25Wr.YSH1 26Rd.YHHP 26Wr.YHHP 27Rd.YHSP 27Wr.YHSP 2Rd.VHH1 2Wr.VHH1 30Rd.YHH1 30Wr.YHH1 33Rd.YSH1 33Wr.YSH1 35Wr.YHH1 36Rd.YHS1 36Wr.YHS1 37Rd.YSH1 37Wr.YSH1 3Rd.VHH1 40Rd.VHH1 40Wr.VHH1 42Rd.YHHP 42Wr.YHHP 43Rd.YHHP 43Wr.YHHP 44Rd.YHS1 44Wr.YHS1 45Rd.YSH1 45Wr.YSH1 46Wr.YHH1 47Rd.YHS1 47Wr.YHS1 48Rd.YSH1 48Wr.YSH1 4Rd.VHH1 4Wr.VHH1 50Rd.YSH1 50Wr.YSH1 53Rd.YSH1 53Wr.YSH1 54Rd.YHH1 54Wr.YHH1 56Rd.YHH1 56Wr.YHH1 59Rd.YHH1 59Wr.YHH1 62Rd.YHSP 62Wr.YHSP 64Rd.YSH1 64Wr.YSH1 65Rd.YHH1

65Wr.YHH1 66Rd.YSS1 66Wr.YSS1 70Rd.YSH1 70Wr.YSH1 71Rd.YHHP 71Wr.YHHP 75Rd.YHH1 75Wr.YHH1 7Wr.YHH1 9Rd.VHH1 9Wr.VHH1

itemSize fifoDepth AvgOfnbTransaction AvgOfnbItem AvgOfactualDelay AvgOfPerf

  • 0,5
  • 0,3
  • 0,1

0,1 0,3 0,5 0,7 0,9

  • 0,9
  • 0,7
  • 0,5
  • 0,3
  • 0,1

0,1 0,3 0,5 0,7 0,9

  • - axe F1 (34 %) -->
  • - axe F2 (23 %) -->

Principal Component Analysis Results on 108 Communication Channels

slide-16
SLIDE 16

16

31

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis - YAPI Application Level Communication

10Rd.VHH1 10Wr.VHH1 11Rd.VHH1 11Wr.VHH1 12Rd.VHH1 12Wr.VHH1 14Rd.YSH1 14Wr.YSH1 16Rd.YHHP 16Wr.YHHP 17Rd.YHHP 17Wr.YHHP 18Rd.YSH1 18Wr.YSH1 19Rd.YSH1 19Wr.YSH1 22Wr.YHHP 23Rd.YHS1 23Wr.YHS1 25Rd.YSH1 25Wr.YSH1 26Rd.YHHP 26Wr.YHHP 27Rd.YHSP 27Wr.YHSP 2Rd.VHH1 2Wr.VHH1 30Rd.YHH1 30Wr.YHH1 33Rd.YSH1 33Wr.YSH1 35Wr.YHH1 36Rd.YHS1 36Wr.YHS1 37Rd.YSH1 37Wr.YSH1 3Rd.VHH1 40Rd.VHH1 40Wr.VHH1 42Rd.YHHP 42Wr.YHHP 43Rd.YHHP 43Wr.YHHP 44Rd.YHS1 44Wr.YHS1 45Rd.YSH1 45Wr.YSH1 46Wr.YHH1 47Rd.YHS1 47Wr.YHS1 48Rd.YSH1 48Wr.YSH1 4Rd.VHH1 4Wr.VHH1 50Rd.YSH1 50Wr.YSH1 53Rd.YSH1 53Wr.YSH1 54Rd.YHH1 54Wr.YHH1 56Rd.YHH1 56Wr.YHH1 59Rd.YHH1 59Wr.YHH1 62Rd.YHSP 62Wr.YHSP 64Rd.YSH1 64Wr.YSH1 65Rd.YHH1 65Wr.YHH1 66Rd.YSS1 66Wr.YSS1 70Rd.YSH1 70Wr.YSH1 71Rd.YHHP 71Wr.YHHP 75Rd.YHH1 75Wr.YHH1 7Wr.YHH1 9Rd.VHH1 9Wr.VHH1

  • 2
  • 1

1 2 3

4

  • 4
  • 3
  • 2
  • 1

1 2

  • - axe F1 (34 %) -->
  • - axe F2 (23 %) -->

Class 1 Class 2 Class 3 Class 5 Class 4

Clustering into Communication Port Classes

32

Conclusions

  • Platform-based design is a reality in several industries

– Particular applications drive particular methodologies

  • Fixed, SW-driven platforms require co-verification approaches

for derivatives

– Automotive example

  • Platform creation can make use of effective design space

exploration methods

– Multimedia example

  • In future, new platform architectures and new co-development

methods may be ‘co-developed’ to allow effective exploitation of architectural features