PID meeting Electronics Integration Christophe Beigbeder PID - - PowerPoint PPT Presentation

Juin 1st 2010 Christophe Beigbeder PID meeting 1

PID meeting

Electronics Integration

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Electronics on the detector

 Mechanical constraints: Fixing the module on the PM base.

Dismounting issues.

 Thermal constraints : Door closed gives problems of cooling.  Fans on the module as G Varner’s ?  Global heat extraction….

Electronics is split in two parts :

• one directly mounted on the PM

base receiving the PM signal and processing it with TDC/ADC

• the other one concentrates and

pack all the channels to send data to the DAQ

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5cm

To DAQ optical 1 Sector -> 48 * 64 = 3072 Channels.

Detector : 12 sectors -> ~ 36 k channels

Cat5 cable

ECS electrical From TTC optical 1 MAPMT footprint = > 64 channels 16 to 128-channel per board

• > 20 to 160 boards per sector.

Concentrator Crate

1 to 12 sectors per crate

Power Supply TDC PGA FE ASIC ADC

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Other possible solutions …

Long boards : 80 channels . Mechanical issues for a precise adjustment base to

• base. This granularity has a impact in case of failure. No long a Pm considered as

a cell element but a row of 5 pms.

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Cooling issue

 A rough estimation gives :

 Fe : 500 mW / 16 channels  Pga : 1 W / 16 channels  TDC : 500 mW /16 channels  ` + glue = > Total 3 W / 16 channels

 = > Sector ( ~ 3Kchannels ) = ~ 600 W  = > 7 KW in total

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Cooling issue

 From documentation

 Q = ( 3.1 P) / T

 Q= airflow in m3 / h  P = Dissipated power ( W)  T = Temperature change at given air flow  -> 600 W power , a specified difference T = 10 degre

requires a airflow of 190 m3 /h

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Mechanical issues

 Boards/ Module insertion/desinsertion issues

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Mechanical constraints

 Pins issue : Male -> Female on the “backplane “

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ADC

12 bits/ 56 Mhz

Jtag

Power Supplies

PM output connectors

FE_Pga

I2C Version 1/03/2010

16 Channels from MaPmt 1 Raw

I2C Regulators/ Delatcher Clock distibution elements ECS

Specs

I2C Probe Output

MUX

TDC

16 Chs 100 ps

*16 (?)

Event Formater ADC

12 bits/

Event Packing

I2C

A c t e l P G A

Fe Asic 16 Channels

Law Walk Discriminator

Sample and Hold Shaper Fast Amp Charge Amp

FE board synopsis

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SNATS : new design

DLL

48 Gray counter 48 bits

DLL @160Mhz Hit

Synchro 5

Clk@160Mhz

Derandomizer Fifo

[1-4 words] *16

Reg Reg 48 7-16 16

Clk@80Mhz

16 *16 5

Packing SNATS2

Sync Data[15:0]@80Mhz

FE Clear Per channel State Machine Global State machine Clear Clear

Instantaneous Dead time Readout dead time

Max speed 1Mhz

Push the data

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Summary of the SNATS evolution :

• Redesign of the readout and a few improvements on the Front end part
• Programmable number of bits for the time counter.
• New derandomizing FIFOs : depth of 16/32 events ( each of 4 * 16-bit data word)
• Data push at the output

Run end 2010 . AMS .35 um technology. Chip delivered first quarter of 2011 We have to think of the way to run the chip together with the FE ASIC and to match the analog pulse converted by the ADC with the hit time -> Design and simulation in the FPGA Also have to interface the FPGA with the Proposa sal for t he e Elec ect ronics s Trigger er and DAQ archit ect ure to get inside the front end buffer. The data are output with a latency depending on the rate per channel and the

• ccupancy of the chip.

2 Clk cycles to output the data ( Derandomizer FIFO to PGA @ 84 MHz (56* 1.5) ) followed by 2 Clk cycles for each other fired Channel. Latency from 2 Clk cycles to 32 Clk cycles ( 2.5 MHz per channel )