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Photonics with Electronics for Opto- Electronic Networks-on-Chip - - PowerPoint PPT Presentation

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DSENT A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun , Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic 5/19/2012 1

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SLIDE 1

DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling

Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic

5/19/2012 1

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SLIDE 2

NoC Cost Evaluation is Critical

Every choice has a cost!

5/19/2012 2

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SLIDE 3

Potential for Photonics

  • Many recent works utilize photonics

Photonics to DRAM [Beamer ‘10, Udipi ‘11] Photonics on-chip [Vantrease ’08, Kurian ‘10]

5/19/2012 3

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SLIDE 4

Potential for Photonics

  • Many recent works utilize photonics

Photonics to DRAM [Beamer ‘10, Udipi ‘11]

  • Tradeoffs of photonics not well explored

Photonics on-chip [Vantrease ’08, Kurian ‘10]

5/19/2012 4

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SLIDE 5

Potential for Photonics

  • Many recent works utilize photonics

Photonics to DRAM [Beamer ‘10, Udipi ‘11]

  • Tradeoffs of photonics not well explored
  • At risk of being too optimistic

Photonics on-chip [Vantrease ’08, Kurian ‘10]

5/19/2012 5

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SLIDE 6

Potential for Photonics

  • Many recent works utilize photonics

Photonics to DRAM [Beamer ‘10, Udipi ‘11]

  • Tradeoffs of photonics not well explored
  • At risk of being too optimistic
  • Device/circuit designers need feedback

Photonics on-chip [Vantrease ’08, Kurian ‘10]

5/19/2012 6

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SLIDE 7

What does a NoC Cost?

5/19/2012 7

Network

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SLIDE 8

Network

What does an NoC Cost?

  • Routers responsible for

directing data

– Digital logic – Consumes power

5/19/2012 8

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SLIDE 9

What does a NoC Cost?

  • Links also consume power
  • Electrical links

– Wire capacitance switching – Repeaters

Network

5/19/2012 9

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SLIDE 10

What does a NoC Cost?

  • Photonic links

– Receivers, Modulators – Laser – Ring thermal tuning – Serialize/Deserialize

Network

5/19/2012 10

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SLIDE 11

What does a NoC Cost?

  • Photonic links

– Receivers, Modulators – Laser – Ring thermal tuning – Serialize/Deserialize

Network

5/19/2012 11

All these costs need to be visible to the network architect!

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SLIDE 12

Existing Architectural Tools

5/19/2012 12

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SLIDE 13

Existing Architectural Tools

5/19/2012 13

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SLIDE 14

Existing Architectural Tools

5/19/2012 14

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SLIDE 15

Existing Architectural Tools

5/19/2012 15

[Joshi, NOCS 2009] [Pan, HPCA 2010]

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SLIDE 16

Existing Architectural Tools

Nothing currently models the interface between electronics and photonics

5/19/2012 16

[Joshi, NOCS 2009] [Pan, HPCA 2010]

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SLIDE 17

Why Not Just Photonics?

5/19/2012 17

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SLIDE 18

Why Not Just Photonics?

  • Original plan for DSENT

, but…

5/19/2012 18

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SLIDE 19

Why Not Just Photonics?

  • Original plan for DSENT

, but…

  • Photonics is dependent on electronics

– Modulator drivers, Receivers – Serialize/Deserialize from core to link – Thermal ring resonance tuning

5/19/2012 19

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SLIDE 20

Why Not Just Photonics?

  • Original plan for DSENT

, but…

  • Photonics is dependent on electronics

– Modulator drivers, Receivers – Serialize/Deserialize from core to link – Thermal ring resonance tuning

  • Need to compare electronics fairly with

photonics…

5/19/2012 20

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SLIDE 21

Orion 2.0 Issues

5/19/2012 21

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SLIDE 22

Orion 2.0 Issues

5/19/2012 22

Scaling factors no longer valid for advanced processes

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SLIDE 23

Orion 2.0 Issues

5/19/2012 23

Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models

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SLIDE 24

Orion 2.0 Issues

5/19/2012 24

Incomplete architectural models and timing for the router Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models

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SLIDE 25

Orion 2.0 Issues

5/19/2012 25

Incomplete architectural models and timing for the router Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models All links are optimized for min-delay

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SLIDE 26

Orion 2.0 Issues

5/19/2012 26

Incomplete architectural models and timing for the router Scaling factors no longer valid for advanced processes Very low accuracies for modern technologies

  • 3X power overestimate for 65 nm, 400 MHz [Jeong, Kahng, et al. 2010]
  • 7X power, 2X area overestimate for 45 nm, 1 GHz
  • 5X+ power overestimate for links
  • Skewed breakdowns

Very difficult to add technology or extend existing models All links are optimized for min-delay

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SLIDE 27

Orion 2.0 Issues

5/19/2012 27

Incomplete architectural models and timing for the router Scaling factors no longer valid for advanced processes Very low accuracies for modern technologies

  • 3X power overestimate for 65 nm, 400 MHz [Jeong, Kahng, et al. 2010]
  • 7X power, 2X area overestimate for 45 nm, 1 GHz
  • 5X+ power overestimate for links
  • Skewed breakdowns

Very difficult to add technology or extend existing models A 10-year-old model that worked well, but insufficient now All links are optimized for min-delay

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SLIDE 28

DSENT

Design Space Exploration of Networks Tool

5/19/2012 28

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SLIDE 29

DSENT

  • Overview

Design Space Exploration of Networks Tool

5/19/2012 29

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SLIDE 30

DSENT

  • Overview
  • Methodology

– Improvements to electrical modeling frameworks – Incorporate photonics models

Design Space Exploration of Networks Tool

5/19/2012 30

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SLIDE 31

DSENT

  • Overview
  • Methodology

– Improvements to electrical modeling frameworks – Incorporate photonics models

  • Example cross-hierarchical network

evaluation Design Space Exploration of Networks Tool

5/19/2012 31

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SLIDE 32

DSENT

  • Overview
  • Methodology

– Improvements to electrical modeling frameworks – Incorporate photonics models

  • Example cross-hierarchical network

evaluation

  • Conclusion

Design Space Exploration of Networks Tool

5/19/2012 32

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SLIDE 33

Structure of DSENT

  • Written in C++ (Object-Oriented)
  • Fast Evaluations, few seconds
  • ASIC-driven approach
  • Made flexible, extensible

5/19/2012 33

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SLIDE 34

Two Ways to Use DSENT

  • Stand-alone for design space exploration

5/19/2012 34

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SLIDE 35

Two Ways to Use DSENT

  • Stand-alone for design space exploration

– Takes network parameters, queries, technology, give back area, power

5/19/2012 35

Technology File Network Parameter File

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SLIDE 36

Two Ways to Use DSENT

  • Stand-alone for design space exploration

– Takes network parameters, queries, technology, give back area, power

5/19/2012 36

Technology File Network Parameter File Run DSENT Results

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SLIDE 37

Two Ways to Use DSENT

  • Use with architectural simulator for app-driven power

traces

  • Uses event counts [Kurian, IPDPS 2012]

5/19/2012 37

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SLIDE 38

DSENT

  • Overview
  • Methodology

– Improvements to electrical modeling frameworks – Incorporate photonics models

  • Example cross-hierarchical network

evaluation

  • Conclusion

Design Space Exploration of Networks Tool

5/19/2012 38

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SLIDE 39

Electrical Model

5/19/2012 39

ASIC-like modeling flow, generates primitives/standard cells

DSENT

User-Defined Models Support Models Tools

Arbiter Router Decoder Buffers Technology Characterization Area Mesh Network Electrical Clos Repeated Link Optical Link Photonic Clos Crossbar Multiplexer Delay Technology Parameters Model Parameters Standard Cells Timing Optimization Expected Transitions Optical Link Components Optical Link Optimization Non-Data- Dependent Power Data-Dependent Energy Nin Nout fclock ... Process VDD Wmin T ...

User Inputs DSENT Outputs

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SLIDE 40

Electrical Model

5/19/2012 40

Keep relevant tech parameters, simplify technology entry ASIC-like modeling flow, generates primitives/standard cells

DSENT

User-Defined Models Support Models Tools

Arbiter Router Decoder Buffers Technology Characterization Area Mesh Network Electrical Clos Repeated Link Optical Link Photonic Clos Crossbar Multiplexer Delay Technology Parameters Model Parameters Standard Cells Timing Optimization Expected Transitions Optical Link Components Optical Link Optimization Non-Data- Dependent Power Data-Dependent Energy Nin Nout fclock ... Process VDD Wmin T ...

User Inputs DSENT Outputs

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SLIDE 41

Electrical Model

5/19/2012 41

Keep relevant tech parameters, simplify technology entry ASIC-like modeling flow, generates primitives/standard cells

DSENT

User-Defined Models Support Models Tools

Arbiter Router Decoder Buffers Technology Characterization Area Mesh Network Electrical Clos Repeated Link Optical Link Photonic Clos Crossbar Multiplexer Delay Technology Parameters Model Parameters Standard Cells Timing Optimization Expected Transitions Optical Link Components Optical Link Optimization Non-Data- Dependent Power Data-Dependent Energy Nin Nout fclock ... Process VDD Wmin T ...

Delay model, timing-constrained cell sizing, electrical links

User Inputs DSENT Outputs

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SLIDE 42

Electrical Model

5/19/2012 42

Keep relevant tech parameters, simplify technology entry ASIC-like modeling flow, generates primitives/standard cells Delay model, timing-constrained cell sizing, electrical links Able to model more generic digital, beyond just routers

DSENT

User-Defined Models Support Models Tools

Arbiter Router Decoder Buffers Technology Characterization Area Mesh Network Electrical Clos Repeated Link Optical Link Photonic Clos Crossbar Multiplexer Delay Technology Parameters Model Parameters Standard Cells Timing Optimization Expected Transitions Optical Link Components Optical Link Optimization Non-Data- Dependent Power Data-Dependent Energy Nin Nout fclock ... Process VDD Wmin T ...

User Inputs DSENT Outputs

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SLIDE 43

Electrical Model

5/19/2012 43

Delay model, timing-constrained cell sizing, electrical links ASIC-like flow, standard cell based Keep relevant tech parameters, simplify technology entry Able to model more generic digital, beyond just routers Methodology targeted for 45 nm and below

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SLIDE 44

Electrical Model

5/19/2012 44

Delay model, timing-constrained cell sizing, electrical links ASIC-like flow, standard cell based Keep relevant tech parameters, simplify technology entry Able to model more generic digital, beyond just routers Power/Area estimates accurate to ~20% of SPICE simulation Methodology targeted for 45 nm and below

Model Reference Point DSENT Router (6x6) Buffer (mW) SPICE – 6.93 7.55 (+9%) Xbar (mW) SPICE – 2.14 2.06 (+4%) Control (mW) SPICE – 0.75 0.83 (+11%) Clock (mW) SPICE – 0.74 0.63 (-15%) Total (mW) SPICE – 10.6 11.2 (+6%) Area (mm2) Encounter – 0.070 0.062 (-11%)

  • 45 nm SOI
  • 6 Input ports, 6 output ports
  • 64-bit flit width
  • 8 VCs/Port, 16 Buffer FIFO
  • 1 GHz clock
  • 0.16 flit injection rate
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SLIDE 45

Photonics Model

  • Four different sources of power consumption

– Modulator, receivers – Laser power – Thermal tuning – Serialize, deserialize backends

5/19/2012 45

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SLIDE 46

Photonics Model

5/19/2012 46

  • Modulator becomes more expensive with:

– High data-rate – Higher modulation depth (extinction ratio) – Lower insertion loss

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SLIDE 47

Photonics Model

5/19/2012 47

  • Receiver becomes more

expensive with:

– High data-rate

  • Receiver sensitivity degrades with:

– High data-rate – Lower modulation depth – Higher bit error rate requirement

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SLIDE 48

Photonics Model

5/19/2012 48

  • Laser power requirement gets worse with:

– Higher receiver sensitivity requirement – Higher channel losses, e.g. higher modulator insertion loss

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SLIDE 49

Photonics Model

5/19/2012 49

  • Ring resonator devices are sensitive to process,

temperature, active tuning is needed

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SLIDE 50

Photonics Model

5/19/2012 50

  • Ring resonator devices are sensitive to process,

temperature, active tuning is needed

  • Not necessarily a fixed cost per ring!

– [Georgas CICC 2011, Nitta HPCA 2011]

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SLIDE 51

Photonics Model

5/19/2012 51

  • Ring resonator devices are sensitive to process,

temperature, active tuning is needed

  • Not necessarily a fixed cost per ring!

– [Georgas CICC 2011, Nitta HPCA 2011]

DSENT models schemes for tuning, impact of process sigmas

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SLIDE 52

Photonics Model

5/19/2012 52

  • Ring resonator devices are sensitive to process,

temperature, active tuning is needed

  • Not necessarily a fixed cost per ring!

– [Georgas CICC 2011, Nitta HPCA 2011]

Serializer/Deserializers are taken care of by electrical framework DSENT models schemes for tuning, impact of process sigmas

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SLIDE 53

DSENT

  • Overview
  • Methodology

– Improvements to electrical modeling frameworks – Incorporate photonics models

  • Example cross-hierarchical network

evaluation

  • Conclusion

Design Space Exploration of Networks Tool

5/19/2012 53

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SLIDE 54

Example Study

  • 256-core clos network, energy per bit as metric

– Pclos, EClos normalized to same throughput/latency

  • 128-bit Flit Width
  • 16 ingress, middle, egress

routers, k, n, r = 16, 16, 16

  • 2 GHz
  • 1 dB/cm waveguide loss

Compare at

  • 45nm (present)
  • 11nm (future)

5/19/2012 54

[Joshi, NOCS 2009]

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SLIDE 55

Two Types of Power

Data-Dependent Non-Data-Dependent Router data-path/control Leakage Electrical links Un-gated clocks Gated clocks Laser Receiver/Modulator Thermal tuning, ring heating SerDes

5/19/2012 55

  • Data-dependent vs. non-data-dependent power
  • Optical components (laser, thermal tuning) are

non-data-dependent

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SLIDE 56

Effect of Utilization

Data-Dependent energy dominant Non-data-dependent energy dominant

5/19/2012 56

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SLIDE 57

Effect of Utilization

Data-Dependent energy dominant Non-data-dependent energy dominant

5/19/2012 57

crossover points

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SLIDE 58

Effect of Utilization

Data-Dependent energy dominant Non-data-dependent energy dominant

5/19/2012 58

Max Throughput Low Throughput

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SLIDE 59

Energy Breakdown at Max Network Throughput (33 Tb/s)

Electrical 45nm Photonic 11nm Photonic 45nm Electrical 11nm

Energy per Bit Breakdown

5/19/2012 59

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SLIDE 60

Energy Breakdown at Max Network Throughput (33 Tb/s)

Electrical 45nm Photonic 11nm Photonic 45nm Electrical 11nm

Energy Breakdown at Low Network Throughput (4.5 Tb/s)

Electrical 45nm Photonic 45nm Photonic 11nm Electrical 11nm

Energy per Bit Breakdown

5/19/2012 60

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SLIDE 61

Energy Breakdown at Max Network Throughput (33 Tb/s)

Electrical 45nm Photonic 11nm Photonic 45nm Electrical 11nm

Energy Breakdown at Low Network Throughput (4.5 Tb/s)

Electrical 45nm Photonic 45nm Photonic 11nm Electrical 11nm

Significant non-data- dependent laser, tuning

Energy per Bit Breakdown

5/19/2012 61

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SLIDE 62

Energy Breakdown at Low Network Throughput (4.5 Tb/s)

Electrical 45nm Photonic 45nm Photonic 11nm Electrical 11nm

Energy per Bit Breakdown

5/19/2012 62

“Wow non-data-dependent laser really hurts, can I make it better?”

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SLIDE 63

Energy Breakdown at Low Network Throughput (4.5 Tb/s)

Electrical 45nm Photonic 45nm Photonic 11nm Electrical 11nm

Energy per Bit Breakdown

5/19/2012 63

Optimistic device guy: “No problem, I go make my devices better!” “Wow non-data-dependent laser really hurts, can I make it better?”

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SLIDE 64

Tech Parameter Study

5/19/2012 64

Evaluate the effect of waveguide losses

“How much better does he need to do in order to beat the competing 11nm electrical?”

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SLIDE 65

Tech Parameter Study

5/19/2012 65

Evaluate the effect of waveguide losses

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SLIDE 66

Tech Parameter Study

5/19/2012 66

Very costly above 1.0 dB/cm

Evaluate the effect of waveguide losses

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SLIDE 67

Tech Parameter Study

5/19/2012 67

Very costly above 1.0 dB/cm Some gains going below 1.0 dB/cm, still can’t win at lower utilizations

Evaluate the effect of waveguide losses

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SLIDE 68

Tech Parameter Study

5/19/2012 68

Very costly above 1.0 dB/cm Some gains going below 1.0 dB/cm, still can’t win at lower utilizations

Evaluate the effect of waveguide losses “Probably need to more than just cut losses on my devices…”

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SLIDE 69

Tech Parameter Study

  • Story doesn’t end here…

5/19/2012 69

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SLIDE 70

Tech Parameter Study

  • Story doesn’t end here…

– Thermal tuning strategies

5/19/2012 70

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SLIDE 71

Tech Parameter Study

  • Story doesn’t end here…

– Thermal tuning strategies – Data-rates, change number of optical devices

5/19/2012 71

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SLIDE 72

Tech Parameter Study

  • Story doesn’t end here…

– Thermal tuning strategies – Data-rates, change number of optical devices – Modulator, laser balance

– Modulator is DD, laser is NDD

5/19/2012 72

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SLIDE 73

Tech Parameter Study

  • Story doesn’t end here…

– Thermal tuning strategies – Data-rates, change number of optical devices – Modulator, laser balance

– Modulator is DD, laser is NDD

  • These are examples of DSENT models

5/19/2012 73

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SLIDE 74

Conclusion

  • Design decisions in NoCs require evaluation

5/19/2012 74

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SLIDE 75

Conclusion

  • Design decisions in NoCs require evaluation
  • We created DSENT to bridge photonics and electronics

– Generalized methodology for digital components – Moves beyond fixed number evaluations for photonics – Includes power/area models for several networks

5/19/2012 75

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SLIDE 76

Conclusion

  • Design decisions in NoCs require evaluation
  • We created DSENT to bridge photonics and electronics

– Generalized methodology for digital components – Moves beyond fixed number evaluations for photonics – Includes power/area models for several networks

  • We showed how DSENT can be used to capture the

tradeoffs for an example photonic clos network

– Utilization-dependent energy plots – Data-dependent and non-data-dependent power – Investigate network sensitivity to optical parameters

5/19/2012 76

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SLIDE 77

Conclusion

  • Design decisions in NoCs require evaluation
  • We created DSENT to bridge photonics and electronics

– Generalized methodology for digital components – Moves beyond fixed number evaluations for photonics – Includes power/area models for several networks

  • We showed how DSENT can be used to capture the

tradeoffs for an example photonic clos network

– Utilization-dependent energy plots – Data-dependent and non-data-dependent power – Investigate network sensitivity to optical parameters

  • Continuing and future work

– Ease user model specification to aid microarchitecture studies – Automatically form estimates for local interconnect

5/19/2012 77

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SLIDE 78

Thank You

For more info, visit https://sites.google.com/site/mitdsent/

(we will make it downloadable following the conference)

5/19/2012 78

  • We would like to acknowledge

– Integrated Photonics teams at MIT and University of Colorado, Boulder for models – Prof. Dmitri Antoniadas’s group for their sub-45nm transistor models

  • Support

– DARPA, NSF , FCRP IFC, SMART LEES, Trusted Foundry, Intel, APIC, MIT CICS, NSERC

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SLIDE 79

Backups

5/19/2012 79

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SLIDE 80

Evaluation Configuration

5/19/2012 80

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SLIDE 81

Evaluation Parameters

5/19/2012 81

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SLIDE 82

Orion Specifics

  • Missing decoder and mux for register-type buffer
  • Flops based on cross-coupled NOR gates

– Uses old Cacti decoder sizing

  • Missing pipeline flops energy on the data-path

– Though clock power of those is added

  • Clock H-tree optimized by data link model

– Optimal delay H-tree

5/19/2012 82

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SLIDE 83

DSENT Modeling Methodology

DSENT

User-Defined Models Support Models Tools

Arbiter Router Decoder Buffers Technology Characterization Area Mesh Network Electrical Clos Repeated Link Optical Link Photonic Clos Crossbar Multiplexer Delay Technology Parameters Model Parameters Standard Cells Timing Optimization Expected Transitions Optical Link Components Optical Link Optimization Non-Data- Dependent Power Data-Dependent Energy Nin Nout fclock ... Process VDD Wmin T ...

5/19/2012 83

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SLIDE 84

Technology Characterization

5/19/2012 84

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SLIDE 85

Optical Models

  • Models for major optical components

– Waveguide, ring, coupler, modulator, photodetecter …

  • Models for peripheral circuitry

– Modulator driver, receiver, SerDes, thermal tuning

External Laser Source Chip

Sender A λ1 λ2 λ1 λ2 Sender B Receiver A Receiver B Ring Modulator with λ1 resonance Ring Modulator with λ2 resonance Single Mode Fiber Coupler Ring Filter with λ1 resonance Ring Filter with λ2 resonance On-chip Waveguide Modulator Driver Receiver Circuit Photodetector λ1 + λ2

5/19/2012 85

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SLIDE 86

Timing Optimization

  • A greedy algorithm to select the standard

cell sizes

– Make circuit meet the timing constraint

...

Delay Delay Delay Delay

...

Delay

...

A-Y

...

A-Y B-Y B-Y A-Y Ron-INV Ron-NAND2 Ron-NAND2 Cin-INV Cin-NAND2 Cin-NAND2

INV NAND2 NAND2

Equivalent Circuit Equivalent Circuit Equivalent Circuit

X Z Z X

Timing Optimization Iteration 1 50 Big Cap 10 25 20 10 200 50 Timing not met! Size up! 1 1 1 35 Timing Optimization Iteration 3 50 Big Cap 10 50 30 20 40 50 Timing not met! Size up! 1 6 55 1 1 Timing Optimization Iteration 4 50 Big Cap 20 35 30 20 40 50 3 6 3 45 1 Timing met! Timing Optimization Iteration 2 50 Big Cap 10 50 45 10 60 50 Size up! 1 6 1 60 1 Timing not met! Timing not met! 3

5/19/2012 86

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SLIDE 87

Expected Transitions

  • A simplified expected transition

probability model

NAND2_X1 Standard Cell Equivalent Circuit A B Y INV_X1 NAND2_X1 Net: B P00 = 0.00 P01 = 0.50 P10 = 0.50 P11 = 0.00 Net: A P00 = 0.30 P01 = 0.20 P10 = 0.20 P11 = 0.30 INV_X1 Standard Cell Net: Y P00 = 0.00 P01 = 0.25 P10 = 0.25 P11 = 0.50 Net: M P00 = 0.30 P01 = 0.20 P10 = 0.20 P11 = 0.30 Leakage Input Gate Cap A Output Drain Cap Calculate Output Transition Leakage Equivalent Circuit Leak(A=0, B=0) Leak(A=0, B=1) Leak(A=1, B=0) Leak(A=1, B=1) Input Gate Cap A Input Gate Cap B Output Drain Cap Calculate Output Transition Leak(A=0) Leak(A=1)

5/19/2012 87

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SLIDE 88

Power Breakdown (Half)

Energy Break-Down at Half Network Throughput (16 Tb/s)

  • Photonics (P45, P11) are

roughly even with electronics

Electrical 45nm Photonic 45nm Photonic 11nm Electrical 11nm

5/19/2012 88

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SLIDE 89

Network Case Study

5/19/2012 89

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SLIDE 90

Photonic Technology Scaling

  • Waveguide loss

5/19/2012 90

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SLIDE 91

5/19/2012 91

  • Ring heating efficiency
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SLIDE 92

Tool Validation (45nm SOI)

Model Reference Point DSENT Orion2.0 + Orion2.0 Mod* Ring Modulator Driver (fJ/b) 50 (11 Gb/s) 60.87 N/A N/A Receiver (fJ/b) 52 (3.5 Gb/s 45nm) 43.02 N/A N/A Router (6x6) Buffer (mW) SPICE – 6.93 7.55 34.4 3.57 Xbar (mW) SPICE – 2.14 2.06 14.5 1.26 Control (mW) SPICE – 0.75 0.83 1.39 0.31 Clock (mW) SPICE – 0.74 0.63 28.8 0.36 Total (mW) SPICE – 10.6 11.2 91.3 5.56 Area (mm2) Encounter – 0.070 0.062 0.129 0.067

+ Default Orion 2.0 technology parameters for 45nm

*Correctly specified 45nm tech params Router (6x6)

  • 6 Input ports, 6 output ports
  • 64-bit flit width
  • 8 VCs/Port, 16 Buffer FIFO
  • 1 GHz clock
  • 0.16 flit injection rate

5/19/2012 92

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SLIDE 93

DSENT Framework

Technology Value Supply Voltage 1.0 V Gate Capacitance / width 1.0 fF/um Effective on current / width 650 uA/um Off-current / width 100 nA/um DIBL 150 mV/V Sub-threshold Swing 100 mV/dec Photodetector Responsivity 1.0 mA/mW … … Primitive Cells NAND2 INVERTER BUFFER … Receiver Modulator …

  • Use only basic

technology parameters

  • Build a usable set of

primitives for modeling

  • Required technology input mostly limited to what is attainable

through ITRS projections and other roadmaps

5/19/2012 93

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SLIDE 94

DSENT Framework

  • Models are defined in

terms other models and primitives

Example Models Mesh Network Clos Network Routers Optical links (SWSR, SWMR) Serializer/Deserializer …

5/19/2012 94

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SLIDE 95

DSENT Framework

  • After initial modeling of

implementation, design can be optimized and evaluated

[Georgas, CICC 2011]

5/19/2012 95

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SLIDE 96

Misc

5/19/2012 96

Error in Cacti 6.5

[S. Li, ICCAD 2011]