Photonics with Electronics for Opto- Electronic Networks-on-Chip - PowerPoint PPT Presentation

DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun , Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic 5/19/2012 1

NoC Cost Evaluation is Critical Every choice has a cost! 5/19/2012 2

Potential for Photonics • Many recent works utilize photonics Photonics on-chip [Vantrease ’08, Kurian ‘10] Photonics to DRAM [Beamer ‘10, Udipi ‘11] 5/19/2012 3

Potential for Photonics • Many recent works utilize photonics Photonics on-chip [Vantrease ’08, Kurian ‘10] Photonics to DRAM [Beamer ‘10, Udipi ‘11] • Tradeoffs of photonics not well explored 5/19/2012 4

Potential for Photonics • Many recent works utilize photonics Photonics on-chip [Vantrease ’08, Kurian ‘10] Photonics to DRAM [Beamer ‘10, Udipi ‘11] • Tradeoffs of photonics not well explored • At risk of being too optimistic 5/19/2012 5

Potential for Photonics • Many recent works utilize photonics Photonics on-chip [Vantrease ’08, Kurian ‘10] Photonics to DRAM [Beamer ‘10, Udipi ‘11] • Tradeoffs of photonics not well explored • At risk of being too optimistic • Device/circuit designers need feedback 5/19/2012 6

What does a NoC Cost? Network 5/19/2012 7

What does an NoC Cost? Network • Routers responsible for directing data – Digital logic – Consumes power 5/19/2012 8

What does a NoC Cost? Network • Links also consume power Electrical links • Wire capacitance switching – Repeaters – 5/19/2012 9

What does a NoC Cost? Network • Photonic links – Receivers, Modulators – Laser – Ring thermal tuning – Serialize/Deserialize 5/19/2012 10

What does a NoC Cost? Network • Photonic links – Receivers, Modulators – Laser – Ring thermal tuning – Serialize/Deserialize All these costs need to be visible to the network architect! 5/19/2012 11

Existing Architectural Tools 5/19/2012 12

Existing Architectural Tools 5/19/2012 13

Existing Architectural Tools 5/19/2012 14

Existing Architectural Tools [Joshi, NOCS 2009] [Pan, HPCA 2010] 5/19/2012 15

Existing Architectural Tools [Joshi, NOCS 2009] [Pan, HPCA 2010] Nothing currently models the interface 5/19/2012 16 between electronics and photonics

Why Not Just Photonics? 5/19/2012 17

Why Not Just Photonics? • Original plan for DSENT , but… 5/19/2012 18

Why Not Just Photonics? • Original plan for DSENT , but… • Photonics is dependent on electronics – Modulator drivers, Receivers – Serialize/Deserialize from core to link – Thermal ring resonance tuning 5/19/2012 19

Why Not Just Photonics? • Original plan for DSENT , but… • Photonics is dependent on electronics – Modulator drivers, Receivers – Serialize/Deserialize from core to link – Thermal ring resonance tuning • Need to compare electronics fairly with photonics… 5/19/2012 20

Orion 2.0 Issues 5/19/2012 21

Orion 2.0 Issues Scaling factors no longer valid for advanced processes 5/19/2012 22

Orion 2.0 Issues Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models 5/19/2012 23

Orion 2.0 Issues Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models Incomplete architectural models and timing for the router 5/19/2012 24

Orion 2.0 Issues Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models Incomplete architectural models and timing for the router All links are optimized for min-delay 5/19/2012 25

Orion 2.0 Issues Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models Incomplete architectural models and timing for the router All links are optimized for min-delay Very low accuracies for modern technologies • 3X power overestimate for 65 nm, 400 MHz [Jeong, Kahng, et al. 2010] • 7X power, 2X area overestimate for 45 nm, 1 GHz • 5X+ power overestimate for links • Skewed breakdowns 5/19/2012 26

Orion 2.0 Issues Scaling factors no longer valid for advanced processes Very difficult to add technology or extend existing models Incomplete architectural models and timing for the router All links are optimized for min-delay Very low accuracies for modern technologies • 3X power overestimate for 65 nm, 400 MHz [Jeong, Kahng, et al. 2010] • 7X power, 2X area overestimate for 45 nm, 1 GHz • 5X+ power overestimate for links • Skewed breakdowns A 10-year-old model that worked well, but insufficient now 5/19/2012 27

DSENT Design Space Exploration of Networks Tool 5/19/2012 28

DSENT Design Space Exploration of Networks Tool • Overview 5/19/2012 29

DSENT Design Space Exploration of Networks Tool • Overview • Methodology – Improvements to electrical modeling frameworks – Incorporate photonics models 5/19/2012 30

DSENT Design Space Exploration of Networks Tool • Overview • Methodology – Improvements to electrical modeling frameworks – Incorporate photonics models • Example cross-hierarchical network evaluation 5/19/2012 31

DSENT Design Space Exploration of Networks Tool • Overview • Methodology – Improvements to electrical modeling frameworks – Incorporate photonics models • Example cross-hierarchical network evaluation • Conclusion 5/19/2012 32

Structure of DSENT • Written in C++ (Object-Oriented) • Fast Evaluations, few seconds • ASIC-driven approach • Made flexible, extensible 5/19/2012 33

Two Ways to Use DSENT • Stand-alone for design space exploration 5/19/2012 34

Two Ways to Use DSENT • Stand-alone for design space exploration – Takes network parameters, queries, technology, give back area, power Technology File Network Parameter File 5/19/2012 35

Two Ways to Use DSENT • Stand-alone for design space exploration – Takes network parameters, queries, technology, give back area, power Technology File Network Parameter File Run DSENT Results 5/19/2012 36

Two Ways to Use DSENT • Use with architectural simulator for app-driven power traces Uses event counts [Kurian, IPDPS 2012] • 5/19/2012 37

DSENT Design Space Exploration of Networks Tool • Overview • Methodology – Improvements to electrical modeling frameworks – Incorporate photonics models • Example cross-hierarchical network evaluation • Conclusion 5/19/2012 38

Electrical Model ASIC-like modeling flow, generates primitives/standard cells User Inputs DSENT Outputs DSENT Model User-Defined Models Area Parameters Arbiter Router Mesh Network Non-Data- N in Dependent Power N out Multiplexer Crossbar Repeated Link Electrical Clos f clock Data-Dependent Decoder Optical Link Photonic Clos Buffers ... Energy Technology Support Models Tools Parameters Optical Link Timing Optimization Process Delay Standard Cells Components V DD W min Expected Optical Link Technology Characterization T Transitions Optimization ... 5/19/2012 39

Electrical Model ASIC-like modeling flow, generates primitives/standard cells Keep relevant tech parameters, simplify technology entry User Inputs DSENT Outputs DSENT Model User-Defined Models Area Parameters Arbiter Router Mesh Network Non-Data- N in Dependent Power N out Multiplexer Crossbar Repeated Link Electrical Clos f clock Data-Dependent Decoder Optical Link Photonic Clos Buffers ... Energy Technology Support Models Tools Parameters Optical Link Timing Optimization Process Delay Standard Cells Components V DD W min Expected Optical Link Technology Characterization T Transitions Optimization ... 5/19/2012 40

Electrical Model ASIC-like modeling flow, generates primitives/standard cells Keep relevant tech parameters, simplify technology entry Delay model, timing-constrained cell sizing, electrical links User Inputs DSENT Outputs DSENT Model User-Defined Models Area Parameters Arbiter Router Mesh Network Non-Data- N in Dependent Power N out Multiplexer Crossbar Repeated Link Electrical Clos f clock Data-Dependent Decoder Optical Link Photonic Clos Buffers ... Energy Technology Support Models Tools Parameters Optical Link Timing Optimization Process Delay Standard Cells Components V DD W min Expected Optical Link Technology Characterization T Transitions Optimization ... 5/19/2012 41

Electrical Model ASIC-like modeling flow, generates primitives/standard cells Keep relevant tech parameters, simplify technology entry Delay model, timing-constrained cell sizing, electrical links Able to model more generic digital, beyond just routers User Inputs DSENT Outputs DSENT Model User-Defined Models Area Parameters Arbiter Router Mesh Network Non-Data- N in Dependent Power N out Multiplexer Crossbar Repeated Link Electrical Clos f clock Data-Dependent Decoder Optical Link Photonic Clos Buffers ... Energy Technology Support Models Tools Parameters Optical Link Timing Optimization Process Delay Standard Cells Components V DD W min Expected Optical Link Technology Characterization T Transitions Optimization ... 5/19/2012 42