Pattern-guided Big Data Processing on Hybrid Parallel Architectures - - PowerPoint PPT Presentation

Pattern-guided Big Data Processing

• n Hybrid Parallel Architectures

Fahad Khalid, Frank Feinbube, and Andreas Polze

Operating Systems and Middleware Group

• Insights from developing simulations for,

– Enumeration of Elementary Flux Modes in Metabolic Networks – Prediction of aftershocks following earthquakes – Prediction of volcanic events – Adiabatic Quantum Computing

• Collaborations

– Max Planck Institute of Molecular Plant Physiology – GFZ German Research Center for Geosciences

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Motivation

• Complications with Hybrid Architectures

– Memory hierarchy per processor type – Designed for high FLOP/s, not Big Data

• Then, assuming the hardware available is hybrid,

– How can we improve both performance and productivity

• f a simulation that requires processing of very large data

sets?

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Motivation

Definitions

• Performance

– Significant speedup

• Productivity

– Ease of development

• Hybrid Architecture

– One or more CPUs = Host – One or more accelerators, e.g., GPUs = Device

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Efficient Hybrid-Resource Utilization (EHRU)

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• Design Approach

– Hierarchical application of patterns for parallel programming

• Expected Outcome

– Improved simulation performance – Improved productivity, by serving as foundation for:

• Frameworks
• Automation tools

Parallel Pipeline Pattern

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Serial processing of stages Pipelined processing of stages 𝑇2 𝑇1 𝑇3 𝑇2 𝑇1 𝑇3 𝑇2 𝑇1 𝑇3

3 1 7 4 9 5 4 3 1 7 4 9 5 4

𝑇2 𝑇1 𝑇3 ⋯ 𝑇2 𝑇1 𝑇3 ⋯

Parallel Pipeline Pattern

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• Simulation as Pipeline

Analytical solutions to 3D Partial Differential Equations in Vectors Numerical solution to a System of Linear Equations Read input data from file Write output data to file

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Data Partitioning

• Motivation

– Main memory and Cache sizes are limited

• Factors affecting partitioning

– Total memory required/available – Impact of partition size on pipeline performance

P1

Out of Memory

P1,1 P1,2 P1,3

OK OK OK

Partition 0 Partition 1 ⋮ Partition 0 Partition 1 ⋮ ⋯ Complete Dataset Chunk

EHRU Pattern Hierarchy

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Hybrid Pipeline

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• Uses of Hybrid Pipelining

– Overlapping computation and communication – Load balancing and optimal resource utilization – Kernel placement based on architecture

⋯ ⋯ ⋯ ⋯ ⋯ ⋯

Hybrid Pipeline Framework (HyPi)

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• HyPi Stages

– DeviceFilter: CUDA Device kernel – CallbackFilter: D2H Communication – PostProcessFilter: Host processing

Device Filter Callback Filter PostProcess Filter Device Filter Callback Filter PostProcess Filter Device Filter Callback Filter PostProcess Filter ⋯ ⋯ ⋯ ⋯ ⋯ ⋯

HyPi & EHRU – Evaluation

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5 10 15 20 25 30 35 40 45 50 55 60 500 million 2 billion 2.5 billion 3.5 billion 4.5 billion 6.3 billion 8.1 billion Time (seconds)

• No. of candidate vectors generated

CPU-only Parallel Custom Pipeline HPF Pipeline

Feasibility and Limitations of EHRU

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• Suitable for

– Dense Linear Algebra – Structured Grids – Monte Carlo

• Not suitable for

– Sparse Linear Algebra – Unstructured Grids – Graph Traversal

Architecture-based Algorithm Decomposition

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• Decompose the algorithm into two

parts:

1. Suitable for execution on the GPU 2. Suitable for execution on the CPU

• CPUs support a diverse range of

kernels

– Everything goes, except for massive parallelism

• How do we decide which part of

the algorithm is suitable for GPUs?

Pattern 𝑜 − 1 Pattern 𝑜 Pattern 1 Pattern 2

⋮

Accelerator CPU Algorithm

Characteristics of Computational Kernels

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• Degree of Parallelism (DoP)

– The amount of parallelism exposed by the kernel

• Arithmetic Intensity

– Ratio of No. of arithmetic instructions to the No. of memory access instructions

• Control Divergence

– No. and complexity of conditional statements

Design Patterns and Algorithm Decomposition

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• Patterns suitable for GPUs

– Map – Stencil

• Patterns NOT suitable for GPUs

– Reduce – Scan – Dynamic Programming

• This categorization is based on Degree of Parallelism

Program Flow with Algorithm Decomposition

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<<Map>> GPU Kernel <<Reduce>> CPU Kernel Intermediate Result

Tool-guided Parallelization for Hybrid Architectures

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• Motivation

– Automatically discerning patterns from serial code – Efficient mapping of parallel code with EHRU

• How?

– Dependence Analysis to discern patterns – Developer feedback to improve affine transformations

• This is work in progress

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• Information Theoretic approach to improve serial to

parallel transformations

• Partitioning for Complex Data structures
• Automated tool for architecture-based algorithm

decomposition

Future Work

Th Thank Yo You!