SLIDE 16
- Simulator: SSDSim[1]
- One workload from MSRC[2] and three workloads from daily collection
- 2 channels, 4 chips per channel and 4 planes per chip
- Comparing these 4 schemes
- Baseline: Normal flash without scheduling, SWL
- SWL[3]: Static wear leveling
- PGIS[4]+SWL: PGIS with native SWL
- Pattern: The proposal
[1] Y. Hu, H. Jiang, D. Feng et al. Exploring and exploiting the multi-level parallelism inside SSDs for improved performance and endurance. IEEE Transactions on Computers, Vol. 62(6):1141–1155, 2013. [2] http://iotta.snia.org/traces/388. [3] Y. Chang, J. Hsieh, and T. Kuo. Improving flash wear leveling by proactively moving static data. IEEE Transactions on Computers, Vol. 59(1):53–65,2010 [4] J. Guo, Y. Hu, B. Mao, and S. Wu. Parallelism and Garbage Collection Aware I/O Scheduler with Improved SSD Performance. In Proceedings of 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS ’2017), pp. 1184–1193, 2017.
Implementation