Overflow in addition and subtraction can happen if?? ta7 What - - PDF document

overflow in addition and subtraction can happen if ta7
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Overflow in addition and subtraction can happen if?? ta7 What - - PDF document

Overflows Overflow in addition and subtraction can happen if?? ta7 What can we do if there is an overflow?? Spring 2006 MIPS support two kinds of arithmetic operations in order to support the two choices


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SLIDE 1

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הנבמ םיבשחמ

ta7

Spring 2006 Amar Lior

Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3rd edition 2

Signed versus unsigned comparison

Supposed register $s0 has the binary

number

1111 1111 1111 1111 1111 1111 1111 1111

And $s1 has:

0000 0000 0000 0000 0000 0000 0000 0000

slt $t0, $s0, $s1 sltu $t0, $s0, $s1

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Bounds Check Shortcut

How can we reduce the cost of checking if

0 <= X < Y

The key is that negative numbers in two’s

complement looks like large numbers in unsigned notation

The most significant bit is a sign bit in tow’s

complement

And it is a large part of the number in the unsigned

notation

The code:

sltu $t0, $a1, $t2 beq $t0, $zero, IndexOutOfBounds

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Overflows

Overflow in addition and subtraction can

happen if??

What can we do if there is an overflow?? MIPS support two kinds of arithmetic operations in

  • rder to support the two choices

Add (add) , add immediate (addi), subtract (sub)

cause exception

Add unsigned (addu), add immediate unsigned (addiu),

subtract unsigned (subu) do not cause exception

C ignore exception so the compiler must use the

  • perations which does not cause exception

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Checking for overflow

IF we still want to detect an overflow we can do:

addu $t0, $t1, $t2 # $t0=sum but don’t trap xor $t3, $t1, $t2 # Check if sign differ slt $t3, $t3, $zero # $t3=1 if sign differ bne $t3, $zero, No_Overflow xor $t3, $t0, $t1 #checking sign of sum slt $t3, $t3, $zero # $t3=1 if sum sign different bne $t3, $zero, Overflow

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Right shift is the same as integer division in power of 2

Suppose we want to divide -5 by 4

The quotient should be -1

The two’s complement representation of -5

1111 1111 1111 1111 1111 1111 1111 1011

If we shift right by 2 bits we will get

0011 1111 1111 1111 1111 1111 1111 1110

The value is 1,073,741,822 instead of -1 The solution??

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ABS ??

addu $s1, $zero, $s2 bgez $s2, 8 sub $s1, $s0, $s2

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ABS??

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Floating point addition is NOT associative

Suppose Then:

. 1 , 10 * 5 . 1 , 10 * 5 . 1

38 38

= = − = z y x

ten ten

. 1 . 1 . . 1 ) 10 * 5 . 1 10 * 5 . 1 ( ) ( . ) 10 * 5 . 1 ( 10 * 5 . 1 ) . 1 10 * 5 . 1 ( 10 * 5 . 1 ) (

38 38 38 38 38 38

= + = + + − = + + = + − = + + − = + +

ten ten ten ten ten ten

z y x z y x

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Floating Numbers in MIPS

The MIPS has a floating point coprocessor It operate on single precision (32-bit) And also on double precision (64-bit) Has its own registers $f0-$f31 Because the registers are only 32-bit wide

Two of them are required to hold doubles To simplify, floating points operations only use

even-numbered registers

Has 8 condition codes flags (cc), 0-7

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Floating-point data movement (MIPS)

Load to coprocessor 1

(base address is an integer register)

lwc1 $f1, 100($s2) l.s and l.d can also be used

Store from coprocessor 1

swc1 $f1, 100($s2) s.s and s.d can also be used

Move from coprocessor 1

mfc1 $f1, $s2

Move to coprocessor 1

mtc1 $s2, $f1

Move inside coprocessor 1

  • move.s $f2, $f4 move.d $f2, $f4

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Floating-Point Instructions in MIPS

MIPS supports the IEEE 754 single precision and

double precision with the following instructions

Addition

single (add.s) double (add.d)

Subtraction

single (sub.s) double (sub.d)

Multiplication single (mul.s) double (mul.d) Division

single (div.s) double (div.d)

Comparison

single (c.x.s) double (c.x.d)

Where x may be equal (eq), not equal (neq), less than

(lt), less than or equal (le), grater than (gt), or grater than or equal (ge)

Branch

true (bc1t) false (bc1f)

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SLIDE 3

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Floating point directives

.float f1,f2,…,fn .double d1,d2,…,dn

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Example

# Converting from # Fahrenheit to calicos # Argument in $f0 # Result in $f12 f2c: l.s $f16, CONST5_F l.s $f18, CONST9_F div.s $f16, $f16, $f18 l.s $f18, CONST32_F sub.s $f18, $f0, $f18 mul.s $f12, $f16, $f18 jr $ra

float f2c (float fahr) { return ((5.0/9.0) * (fahr – 32.0)); }

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Parallel operations

MIPS-32 added “paired single” version of all

floating point instructions

A single instruction results in two parallel

floating point operations on two 32-bit

  • perands

Example add.ps F0, F2, F4 is equivalent to

add.s F0, F2, F4 add.s F1, F3, F5

The intel SSE2 (Streaming SIMD Extension

2) is similar

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The Floating-point bug

The Pentium FDIV bug is the most famous (or

infamous) of the Intel microprocessor bugs.

It was caused by an error in a lookup table that

was a part of Intel's SRT algorithm that was to be faster and more accurate.

With a goal to boost the execution of floating-point

scalar code by 3 times and vector code by 5 times, compared to the 486DX chip

Intel decided to use the SRT algorithm that can

generate two quotient bits per clock cycle, while the traditional 486 shift-and-subtract algorithm was generating only one quotient bit per cycle.

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The Floating-point bug

This SRT algorithm uses a lookup table to calculate

the intermidiate quotients necessary for floating- point division.

Intel's lookup table consists of 1066 table entries,

  • f which, due to a programming error, five were

not downloaded into the programmable logic array (PLA).

When any of these five cells is accessed by the

floating point unit (FPU), it (the FPU) fetches zero instead of +2, which was supposed to be contained in the "missing" cells.

This throws off the calculation and results in a less

precise number than the correct answer

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At its worst, this error can occur as high as

the fourth significant digit of a decimal number

but the possibilities of this happening are 1

in 360 billion.

It is most common that the error appears in

the 9th or 10th decimal digit

which yields a chance of this happening of 1

in 9 billion.

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SLIDE 4

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July 1994: Intel discovers the bug. The

actual cost to fix was several hundred $$

Intel decided not to fix but to wait until a

new version of the processor comes out in January 1995

September 1994: A math professor at

Lynchburg College in Virginia, Thomas Nicely discovers the bug

November 7, 1994 Electronic Engineering

Times puts the story in his front page …

20 November 22, 1994: Intel issue a press release calling the

bug a glitch …

December 5, 1994: Intel claims the flow happens once in

27,000 years for the typical spreadsheet user

December 12, 1994: IBM Research Division disputes Intel’s

calculation claiming an error as often as once every 24 days

IBM stops shipment of all IBM personal computers based on this chip

December 21, 1994: Intel decide to replace any faulty chip

free of charge asking no questions ….

Analysts estimate this recall cost Intel $500 million