Number Units in Multi-Core Clusters ARITH 2016 Silicon Valley July - - PowerPoint PPT Presentation

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Number Units in Multi-Core Clusters ARITH 2016 Silicon Valley July - - PowerPoint PPT Presentation

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Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters ARITH 2016 Silicon Valley July 10-13, 2016 Michael Schaffner 1 Michael Gautschi 1 Frank K. Grkaynak 1 Prof. Luca Benini 1,2 1 Integrated Systems Laboratory

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1Integrated Systems Laboratory 2 Università di Bologna

Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters

ARITH 2016 Silicon Valley July 10-13, 2016

Michael Schaffner1 Michael Gautschi1 Frank K. Gürkaynak1

  • Prof. Luca Benini1,2
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Integrated Systems Laboratory

Sense Analyze and Classify Transmit Complex preprocessing close to sensor, e.g.: Feature extraction, regression, classification, compression, sensor fusion Low Power Processing System

Advanced Processing in IoT

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  • Fixed-point: labor intensive, error-prone, quality losses

Fixed-Point 1 - 10 mW Low Power Processing System 100 µW - 2 mW Idle: ~1µW Active: ~ 50mW

Arithmetic with High Dynamic Range (HDR) Desirable

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  • Fixed-point: labor intensive, error-prone, quality losses
  • Energy-efficient, low-cost HDR arithmetic desirable

Low Power Processing System 100 µW - 2 mW Idle: ~1µW Active: ~ 50mW

Arithmetic with High Dynamic Range (HDR) Desirable

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HDR Arithmetic 1 - 10 mW

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Integrated Systems Laboratory

Logarithmic Number System (LNS)

  • Efficient MUL, DIV, SQRT
  • c = log2(2a */ 2b) = log2(2a ±b) = a ±b
  • c = log2(sqrt(2a)) = log2(20.5a) = 0.5a = a >> 1

→ Simple integer operations!

  • Nonlinear ADD, SUB, I2F, F2I
  • function interpolator → large LNS unit (LNU)

1 8 23

LNS: fixed-point exponent FP: integer exponent FP: integer mantissa

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Integrated Systems Laboratory

  • Bilateral filter example:
  • Error tolerant applications
  • Full precision not always required

→ Additional tuning knob

Precision & Approximation

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LNS 8.23 (0.5ulp) “precise” LNS 8.17 (16 ulp) “approximate”

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Integrated Systems Laboratory

Contributions

  • Generator framework for automatic generation of “precise” (0.5ulp)

and “approximate” (> 0.5ulp) LNU instances.

  • Design space exploration of precise / approximate LNUs.
  • 33%-71% smaller LNU (precise) with more functionality than previous

designs [8,9,27].

  • Case study: accuracy/performance tradeoffs of a shared LNU in a

65nm CMOS multicore cluster.

[8] J.N. Coleman et al. "The European Logarithmic Microprocessor" IEEE TC, 2008 [9] R.C. Ismail et al. "ROM-less LNS" IEEE ARITH, 2011 [27] M. Gautschi, M. Schaffner, F.K. Gürkaynak, L. Benini, ISSCC 2016

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Problematic LNS Additions/Subtractions

  • C=A ±B with

A = 2a, B = 2b, C = 2c

  • Easy case (ADD): c = log2(2a + 2b) = max(a,b) + f +(|a-b|)
  • Hard case (SUB): c = log2(2a - 2b) = max(a,b) + f -(|a-b|)

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critical region

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Critical Region Decomposition

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  • Analytic transformation of f - into subfunctions
  • Literature:

– Coleman (1995) [5] – Arnold (1998) [4] – Vouzis (2007) [7] – Coleman (2008) [8] – Ismail (2011) [9] – Gautschi, Popoff (2016) [27,11] – This work, using Paliouras (1996) [3]

94 kGE 63 kGE 40 kGE 27 kGE ASIC complexity 8.23bit, 0.5ulp (Synthesis):

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Critical Region Decomposition

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cotrans(r) c = max(a,b) + f -(r) c = max(a,b) - log2((1-2-r) / r) + log2(r)

critical region

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Function Approximation

f (r)

r

  • E.g., 8.23 LNS
  • Different methods:

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r

Interpolation error 1st order 2nd order 3rd order

f (r) f (r)

r

1) LUT only (very large!) 2) High order polynomial

  • Often high order required
  • Large interpolator delay

3) LUT + piecewise poly

  • Tradeoff: precomputation vs. interpolation
  • Half precision - single precision: 1-2nd order

d d d d

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LNU Generator Framework

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  • Specs: bitwidth, accuracy, order
  • Iterative fitting heuristic (similar to [30])
  • Piecewise minimax polynomials (using Sollya [29])

[30] De Dinechin et al., “Automatic Generation of Polynomial-Based Hardware Architectures for Function Evaluation”, ASAP 2010 [29] Chevillarde et al., “Sollya: An Environment for the Development of Numerical Codes”, ICMS 2010

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Architecture Template

Preprocessing Block Postprocessing Block Main Interpolator Block

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Log/Exp Block

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LNS Sub (critical):

Postprocessing Block Main Interpolator Block

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Log/Exp Block c = max(a,b) + cotrans(r)+ log2(r)

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LNS Sub (critical):

Postprocessing Block

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Log/Exp Block c = max(a,b) + cotrans(r)+ log2(r) LUTs Nth order interpolator

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LNS Sub (critical):

Postprocessing Block

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c = max(a,b) + cotrans(r)+ log2(r)

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LNS Sub (critical):

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c = max(a,b) + cotrans(r)+ log2(r)

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“Precise” 32bit LNU: Features & Comparison

ELM [8] ROM-less [9] ISSCC’16 [27] This Work Functionality ADD, SUB ADD, SUB F2I, I2F, EXP, LOG, ADD, SUB F2I, I2F, EXP, LOG, ADD, SUB Max error [ulp] 0.454 0.498 0.479 0.45 LUT size [Kbit] 256.4 183.3 113.1 64.2 Technology 180 nm 180 nm 65 nm 65 nm Area [um2] 904’943 589’357 57’264 38’592 Post-synthesis [kGE] 97 63 40 26.8 Min delay [ns] 11.74 7.10 6 4.5 Max delay [ns] 13.15 14.79 6 4.5

[8] J.N. Coleman et al. "The European Logarithmic Microprocessor" IEEE TC, 2008 [9] R.C. Ismail et al. "ROM-less LNS" IEEE ARITH, 2011 [27] M. Gautschi, M. Schaffner, F.K. Gürkaynak, L. Benini, ISSCC 2016

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Design Space: Precision vs. Area

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Tipping point 1st → 2nd order

  • 40%

@4.5ns delay in umc65, post-synthesis ulp in the LNS domain

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Case Study: HW Platform

  • Parallel Ultra-Low-Power (PULP) Platform [31]

 4x 32b OpenRISC Cores (in-order)  16 kByte shared L1 (TCDM), 16 kByte L2 memory

  • Configurations:

– 1 Shared LNU (Precise, Approx1, Approx2)

  • 4, 3 or 2 pipeline registers
  • Fair round robin arbiter

– 4 Private FPUs (reference)

  • Directly integrated into cores
  • 2 pipeline register

[31] M. Gautschi et al., “Tailoring Instruction-Set Extensions for an Ultra-Low Power Tightly-Coupled Cluster of OpenRISC Cores,” in VLSI-SoC, 2015

LNU PE0 PE1 PE3 PE2 PE0 PE1 PE3 PE2

FPU FPU FPU FPU

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www.pulp-platform.org

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Chip Complexities

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Name Format Bitwidth Precision Order Pipeline Stages FPU/LNU [kGE] Total Complexity [kGE] FPU IEEE754 8.23 0.5 ulp

  • 2

4x11 720 Precise LNS 8.23 0.5 ulp 2 4 36 718 Approx1 LNS 8.20 4 ulp* 2 3 27 708 Approx2 LNS 8.17 16 ulp* 1 2 23 704 * In the LNS domain

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Kernel Level Results

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Pipeline depth is the relevant factor! Energy efficiency gains mainly due to corresponding speedup!

umc65, post-layout

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Conclusions

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  • Generator Framework for precise and approximate LNUs
  • Very compact 8.23bit LNU (33%-71% smaller)
  • Shared setting attractive for LNU
  • Up to 4.2x more energy efficient than private FPU baseline
  • Approximation:
  • Additional gains in area, speedup and energy efficiency
  • Energy-efficiency gains mainly due to lower latency and speedup
  • Less time is needed to complete a task → lower system energy consumption
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PULP Platform: Looking for Collaborators! Outlook

  • Vectorization and trigonometric extensions
  • Optimization opportunities for many algorithms

to leverage LNS and approximation

  • OpenRISC / RISC-V ISA
  • Open source, silicon proven
  • Extending DSP capabilities…
  • www.pulp-platform.org

pulp@pulp.ethz.ch

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Q&A

Acknowledgements:

Nano Tera IcySoC project

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Backup Slides

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Outline

  • Motivation
  • Preliminaries: LNS Add/Sub and Interpolation
  • LNU Architecture and Generator Framework
  • Multicore Hardware Platform
  • Results
  • Conclusion
  • Q&A

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Core 0 Core 1 Core 2 Core 3 FPU FPU FPU FPU INT operations HDR-ADD/SUB/MUL

Private FPUs

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50%

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Core 0 Core 1 Core 2 FPU Core 3 INT operations LNU

  • Area: 1 LNU < 4× standard IEEE compliant FPU (no DIV)
  • Poor LNU utilization ~ 0.2

FPU LNU FPU LNU FPU LNU HDR MUL/DIV/SQRT ADD/SUB

Private LNUs

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Shared LNU

Core 0 Core 1 Core 2 Core 3 Core 0 Interconnect Arbiter LNU INT operations HDR-MUL/DIV/SQRT HDR-ADD/SUB/I2F/F2I

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Design Space Exploration

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  • Bitwidth:

– Half to Single Precision: 5.10 – 8.23

  • Accuracy:

– Precise (0.5ulp) and Approximate (up to 16ulp)

  • Order:

– 1st/2nd Order Interpolation

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Design Space: Area vs. Delay

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Precise Approx2 Approx1 * Required # pipeline stages for 500MHz target * *

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Kernels

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  • Linear Algebra: AXPY, GEMM, GEMV, DotP
  • Matrix Factorizations: Chol, QR
  • Geometry: Homographies, Distances, Pojection Errors
  • Image: Gradient Magnitude, Bilateral, FIR
  • Audio: Butterworth, Sine, DCT-II
  • Other: Radial Basis Functions

50% 25%

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LNU PULP Chips

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Selene (ISSCC’16 [27]) UMC 65nm 4 OpenRISC Cores 1 shared 32bit LNU Phoebe UMC 65nm 4 OpenRISC Cores 1 shared 32bit LNUv2 1 shared 2x16bit LNUv2

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Comparison with SFU

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Functionality Format Functionality Precision Order NaN, INF support Postlayout [kGE] Caro et al. 2009 SQRT, INVSQRT, INV, LOG, EXP, SQRT2, INVSQRT2 IEEE754, 8.23 8.23 1.0 ulp 2 no 36.3 LNU ADD, SUB, F2I, I2F, LOG, EXP, INV*, INVSQRT*, SQRT* LNS, 8.23 8.23 0 - 0.75 ulp 2 yes 36

  • D. D. Caro, N. Petra, and A. G. M. Strollo, “High-Performance Special Function Unit for Programmable 3-D

Graphics Processors,” IEEE TCAS I, vol. 56, no. 9, pp. 1968–1978, Sept 2009.

* Evaluated in integer cores

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PULP Architecture with shared LNU

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4 Core Cluster and L1 Memory Periphery and L2 Memory

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PULP Architecture with shared LNU

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33.3333.. = (-1)0 * (1 + 0.0416666) * 25 33.3333.. = (-1)0 * 25.0588936

IEEE 754 float LNS 01000010000001010101010101010101 00000010100001111000100111010100 LNS Example

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Accuracy Impact (1)

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Accuracy Impact (2)

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