More Moores Law through More Moore s Law through Computational - - PowerPoint PPT Presentation

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More Moores Law through More Moore s Law through Computational - - PowerPoint PPT Presentation

NSF DA Workshop - July 8 2009 NSF DA Workshop July 8, 2009 More Moores Law through More Moore s Law through Computational Scaling -- and EDAs Role d EDA R l David Z. Pan Dept. of Electrical and Computer Engineering The University


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SLIDE 1

NSF DA Workshop - July 8 2009

More Moore’s Law through

NSF DA Workshop July 8, 2009

More Moore s Law through Computational Scaling d EDA’ R l

  • - and EDA’s Role

David Z. Pan

  • Dept. of Electrical and Computer Engineering

f The University of Texas at Austin dpan@ece.utexas.edu http://www cerc utexas edu/utda

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http://www.cerc.utexas.edu/utda

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SLIDE 2

Scaling & Lithography Status

10 10 1

[Courtesy Intel]

  • nce

1 0 1 um 0.1 1980 1990 2000 2010 2020

 193nm litho continues to push its limit

[Courtesy Intel, 2006]

p

› Immersion, extreme RET, DPL (Double Patterning Lithography)

 NGL - Next Generation Lithography, still next generation

E i l/ t i l/t h i l h ll

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› Economical/material/technical challenges

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SLIDE 3

A Famous (or Infamous?) Projection

DFM to Rescue

[Courtesy Synopsys] [Courtesy Synopsys]

 Scaling, though challenged, still pushing!

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 But more important role in computational scaling

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SLIDE 4

Computational Scaling

 Not just by equipment advancement  Computational scaling

› Scaling enabled by massive computational power › Fast computers to help design faster computers

 Computational lithography for nanolithography

systems

C t ti ll i i › Computationally reverse-engineering

 Electronic design automation (EDA) eco-system

to close the gaps to close the gaps

› Synergistic Process-Layout-Circuit Co-Optimization › Parallel multi-core GPU domain-specific FPGA

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› Parallel, multi core, GPU, domain specific, FPGA…

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SLIDE 5

Computational Lithography

[Si h+ SPIE’08)

Intel’s Pixelated Mask

[Singh+, SPIE’08)

 Other examples:

› Variational litho-modeling [Yu+, DAC’06, JM3’07]

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› IBM: source mask optimization

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SLIDE 6

Computational Nanolithography

 We do have massive computational power!

› IBM BlueGene, Brion/ASMLTachyon (FPGA l ti ) G d (l i h GPU) acceleration), Gauda (leveraging cheap GPU), …

 Make a trillion pixels dance [Singh+, SPIE’08]

There's Plenty of Room at the Bottom Still There's Plenty of Room at the Bottom

  • An Invitation to Enter a New Field of Physics

Richard P. Feynman, 1959

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SLIDE 7

Synergistic Process-Layout-Ckt Co-Opt

Higher Level Opt. Shape/Electrical Optimization g p DFM Clock Syn. DFM P & R DFM Cell Lib/Fabric

Predictive Modeling

OPC/RET DFM Cell Lib/Fabric

Predictive Modeling

  • Var. Si-image Model
  • Var. Electrical Model

Shape/Electrical Analysis

(litho, CMP, etc)

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SLIDE 8

Synergistic Optimizations

 Need good levers at different levels of

abstraction for process/layout/circuit co-opt.

Design

“Give me a place to stand on, and I can move the earth ” Archimedes’ Lever

Lever EDA Design

“Give me a lever, and I can optimize your billion i d i ” EDA’ L ( d l/ l ) earth.

  • Archimedes Lever

Lever

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transistor design.” - EDA’s Lever (model/rule)

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SLIDE 9

Process Modeling

 How complicated?

' ' ' '

( ) ( ) ( ) ( ) I x y J x x y y F x y F x y

  

1 1 ' ' ' ' 1 1 1 1

( ) ( ) ( ) ( ) ( ) ( )

I

I x y J x x y y F x y F x y K x x y y K x x y y dx dy dx dy

             

 

Litho model: Hopkins eqn  or simple can it be?

) 1 ( *

2

density Metal Th k C

CMP model:  Key Issues:

) _ 1 ( * _   density Metal Thickness Cu  

[Cho+, ICCAD’06]  Key Issues:

› Accuracy vs. Fidelity (Elmore-like) › Design-oriented vs. process-oriented

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g p

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SLIDE 10

Prediction & Prescription

Layout! Hotspot! y

 Prediction: e.g., statistical modeling [Cho+, DAC’08],

machine learning [Ding+, ICICDT’09]

 Prescription: only work with patterns that are printable

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 Prescription: only work with patterns that are printable

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SLIDE 11

E.g., Post-OPC Predictive Modeling

0.6 0.8 1 n Result

[Cho+, DAC’08]

0.2 0.4 0.6 Simulation

Higher correlation in more macro level,

0.2 0.4 0.6 0.8 1 Litho Metric 0.4 0.6 0.8 1 ation Result

R=0.90, 16x16um2

0.2 0.4 0.6 0.8 1 0.2 0.4 Simulati Litho Metric 0.2 0.4 0.6 0.8 1 Litho Metric

R=0.95, 32x32um2  Very high macro-level fidelity

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y g y

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SLIDE 12

Moving Up: System/High-Level and Logic/Physical-Level Co-design

System High-Level Logic Physical Level Co-design

System Profiling Variation Modeling

Synthesis planning Design guidance from physical reality  Variation budgeting with system-level profiling  Variation budgeting with system level profiling

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SLIDE 13

Moving Dow n: Design for Equipment

Equipment Characteristics Tunable Parameters

 Timing optimization using ASML dose mapper [Jeong,

Kahng+ DAC’08]

 Combine DFM and APC (advanced process control)

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 Combine DFM and APC (advanced process control)

[Pan+, JPC’08]

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SLIDE 14

The Moore, The Better

 There is still plenty of life for Moore’s Law  Bigger role of Computational Scaling and EDA

t t d th M ’ L to extend the Moore’s Law

 NO EXPONENTIAL IS

FOREVER…

 BUT  WE CAN DELAY

“FOREVER”

Moore’s Law Amendment [Moore 2003]

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[Moore 1965] [Moore 2003]