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SBU - Tehran ENSL - Lyon Modulo- Parallel Prefix Addition via Excess-Modulo Encoding of Residues Seyed Hamed Fatemi Langroudi & Ghassem Jaberipur Computer Science & Engineering Department Shahid

slide-1
SLIDE 1

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residues

Seyed Hamed Fatemi Langroudi & Ghassem Jaberipur Computer Science & Engineering Department Shahid Beheshti University, Tehran, Iran

1

SBU - Tehran ENSL - Lyon

22 th IEEE symposium on Computer Arithmetic

Prepared by :Hamed Fatemi

slide-2
SLIDE 2

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

  • Contribution
  • RNS in General
  • Summery of Modulo Addition
  • New Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 Adders
  • Comparison
  • Conclusion

2

ARITH 22

Outline

slide-3
SLIDE 3

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Contribution

ARITH 22

slide-4
SLIDE 4

Modulo Delay(βˆ†π‘―) Area(𝓑𝑯) EM Encoding

2π‘œ βˆ’ 1 ,3- 3 + 2 log π‘œ 3π‘œ log π‘œ + 4π‘œ

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo-addition

Contribution

ARITH 22

slide-5
SLIDE 5

Modulo Delay(βˆ†π‘―) Area(𝓑𝑯) EM Encoding

2π‘œ βˆ’ 1 ,3- 3 + 2 log π‘œ 3π‘œ log π‘œ + 4π‘œ

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo-addition

Contribution

ARITH 22

2π‘œ βˆ’ 3 ,13- 4 + 2 log π‘œ 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 *0, 1, 2+

slide-6
SLIDE 6

Modulo Delay(βˆ†π‘―) Area(𝓑𝑯) EM Encoding

2π‘œ βˆ’ 1 ,3- 3 + 2 log π‘œ 3π‘œ log π‘œ + 4π‘œ

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo-addition

Contribution

ARITH 22

2π‘œ βˆ’ 3 ,13- 4 + 2 log π‘œ 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 *0, 1, 2+ 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 ,10- 7 + 2 log π‘œ ≀ 3π‘œ log π‘œ + 7π‘œ βˆ’ 1 + 1.5(π‘œ βˆ’ 3) log(π‘œ βˆ’ 3)

none

slide-7
SLIDE 7

Modulo Delay(βˆ†π‘―) Area(𝓑𝑯) EM Encoding

2π‘œ βˆ’ 1 ,3- 3 + 2 log π‘œ 3π‘œ log π‘œ + 4π‘œ

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo-addition

Contribution

ARITH 22

2π‘œ βˆ’ 3 ,13- 4 + 2 log π‘œ 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 *0, 1, 2+ 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 ,10- 7 + 2 log π‘œ ≀ 3π‘œ log π‘œ + 7π‘œ βˆ’ 1 + 1.5(π‘œ βˆ’ 3) log(π‘œ βˆ’ 3)

none

2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 5 + 2 log π‘œ ≀ 3π‘œ log π‘œ + 7π‘œ βˆ’ 1 + 1.5 π‘œ βˆ’ 3 log π‘œ βˆ’ 3 +π‘œ βˆ’ 3 log π‘œ βˆ’ 4 ,0,2π‘Ÿ-

slide-8
SLIDE 8

Modulo Delay(βˆ†π‘―) Area(𝓑𝑯) EM Encoding

2π‘œ βˆ’ 1 ,3- 3 + 2 log π‘œ 3π‘œ log π‘œ + 4π‘œ

3 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo-addition

Contribution

ARITH 22

2π‘œ βˆ’ 3 ,13- 4 + 2 log π‘œ 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 *0, 1, 2+ 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 ,10- 7 + 2 log π‘œ ≀ 3π‘œ log π‘œ + 7π‘œ βˆ’ 1 + 1.5(π‘œ βˆ’ 3) log(π‘œ βˆ’ 3)

none

2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 5 + 2 log π‘œ ≀ 3π‘œ log π‘œ + 7π‘œ βˆ’ 1 + 1.5 π‘œ βˆ’ 3 log π‘œ βˆ’ 3 +π‘œ βˆ’ 3 log π‘œ βˆ’ 4 ,0,2π‘Ÿ-

𝐡 new ≀ 𝐡(,10-) π‘œ ≀ 16

slide-9
SLIDE 9
  • RNS in General

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-10
SLIDE 10
  • RNS in General
  • e.g.

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-11
SLIDE 11
  • RNS in General
  • e.g.
  • RNS Architecture

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

X

z1 z2 z3

Z

Binary to RNS x1 x2 x3 y1 y2 y3

Modulo 3

  • peration

Modulo 4

  • peration

Modulo 5

  • peration

RNS to Binary

Y

(e.g.,{3,4,5})

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-12
SLIDE 12
  • RNS in General
  • e.g.
  • RNS Architecture

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

X

z1 z2 z3

Z

Binary to RNS x1 x2 x3 y1 y2 y3

Modulo 3

  • peration

Modulo 4

  • peration

Modulo 5

  • peration

RNS to Binary

Y

7 23

(e.g.,{3,4,5})

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-13
SLIDE 13
  • RNS in General
  • e.g.
  • RNS Architecture

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

X

z1 z2 z3

Z

Binary to RNS x1 x2 x3 y1 y2 y3

Modulo 3

  • peration

Modulo 4

  • peration

Modulo 5

  • peration

RNS to Binary

Y

7 2 3 3 1 3 2 23

(e.g.,{3,4,5})

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-14
SLIDE 14
  • RNS in General
  • e.g.
  • RNS Architecture

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

X

z1 z2 z3

Z

Binary to RNS x1 x2 x3 y1 y2 y3

Modulo 3

  • peration

Modulo 4

  • peration

Modulo 5

  • peration

RNS to Binary

Y

7 2 3 3 1 3 2

Modulo 3 Addition Modulo 4 Addition Modulo 5 Addition

23

(e.g.,{3,4,5})

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-15
SLIDE 15
  • RNS in General
  • e.g.
  • RNS Architecture

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

X

z1 z2 z3

Z

Binary to RNS x1 x2 x3 y1 y2 y3

Modulo 3

  • peration

Modulo 4

  • peration

Modulo 5

  • peration

RNS to Binary

Y

7 2 3 3 1 3 2

Modulo 3 Addition Modulo 4 Addition Modulo 5 Addition

2 30 23

(e.g.,{3,4,5})

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-16
SLIDE 16
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-17
SLIDE 17
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+

slide-18
SLIDE 18
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-19
SLIDE 19
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-20
SLIDE 20
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage
  • Comparison & Division

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-21
SLIDE 21
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage
  • Comparison & Division
  • RNS In Application

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-22
SLIDE 22
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage
  • Comparison & Division
  • RNS In Application
  • Digital Signal Processing

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-23
SLIDE 23
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage
  • Comparison & Division
  • RNS In Application
  • Digital Signal Processing
  • Fault Tolerant System

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-24
SLIDE 24
  • RNS in General
  • e.g.
  • RNS Architecture
  • RNS Advantage
  • Addition & Multiplication
  • RNS Disadvantage
  • Comparison & Division
  • RNS In Application
  • Digital Signal Processing
  • Fault Tolerant System
  • Cryptography

4

𝑆 = *π‘›π‘™βˆ’1, … , 𝑛1, 𝑛0}, 𝐸𝑆 = 𝑛𝑙

𝑗=π‘™βˆ’1 𝑗=0

π‘Œπœ—π‘†, π‘Œ = ( π‘Œ π‘›π‘™βˆ’1, … , π‘Œ 𝑛1, π‘Œ 𝑛0)

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 𝑺 = *πŸ‘π’ βˆ’ 𝟐, πŸ‘π’, πŸ‘π’ + 𝟐+ O log(

π‘œ 𝑙)

slide-25
SLIDE 25

5 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 1 ARITH 22

slide-26
SLIDE 26

5 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 1

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 1 π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 1

Conventional ARITH 22

slide-27
SLIDE 27

5 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 1

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 1 π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 1

Conventional

Adder A Adder B

Mux

2 n

X Y 

2 2

1  

n n

X Y

A

C

B

C

X Y

1

1

2 1 ο€­



n

X Y

RCA ARITH 22

slide-28
SLIDE 28

5 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 1

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 1 π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 1

Conventional EM Encoding

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

1  

n n

X Y

A

C

B

C

X Y

1

1

2 1 ο€­



n

X Y

RCA ARITH 22

slide-29
SLIDE 29

5 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 1

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 1 π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 1

Conventional EM Encoding

π‘Œ + 𝑍 2π‘œβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

1  

n n

X Y

A

C

B

C

X Y

1

1

2 1 ο€­



n

X Y

Adder

  • ut

C

X Y

n

2 1

X Y

ο€­



RCA RCA ARITH 22

slide-30
SLIDE 30

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

slide-31
SLIDE 31

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN)

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

slide-32
SLIDE 32

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN)

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

p g h

οƒ… x y xy οƒš x y

x

y

slide-33
SLIDE 33

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN)

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

slide-34
SLIDE 34

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN)

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

 

, G P

 

,

r r

G P ( )

r

G P G οƒš

slide-35
SLIDE 35

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN)

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

( , )

r r

G P G P P οƒš

 

, G P

 

,

r r

G P

 

, G P

 

,

r r

G P ( )

r

G P G οƒš

slide-36
SLIDE 36

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN) Modulo- 2π‘œ βˆ’ 1 EM Encoding Parallel prefix Adder

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

( , )

r r

G P G P P οƒš

 

, G P

 

,

r r

G P

 

, G P

 

,

r r

G P ( )

r

G P G οƒš

slide-37
SLIDE 37

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN) Modulo- 2π‘œ βˆ’ 1 EM Encoding Parallel prefix Adder

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

c3 c4 c5 c6 h3 c7 h4 h5 h6 h7 h2 c2 c1 h1 pgh pgh pgh h0

G7:0

(G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0)(G1:0,P1:0) (G0:0,P0:0)

s0 s1 s2 s3 s4 s5 s6 s7

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

( , )

r r

G P G P P οƒš

 

, G P

 

,

r r

G P

 

, G P

 

,

r r

G P ( )

r

G P G οƒš

slide-38
SLIDE 38

6 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Parallel Prefix Realization

Parallel Prefix Network(PPN) Modulo- 2π‘œ βˆ’ 1 EM Encoding Parallel prefix Adder

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0 (g0,p0) (g1,p1) (g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g7,p7) G7:0

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

c3 c4 c5 c6 h3 c7 h4 h5 h6 h7 h2 c2 c1 h1 pgh pgh pgh h0

G7:0

(G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0)(G1:0,P1:0) (G0:0,P0:0)

s0 s1 s2 s3 s4 s5 s6 s7

 

, G P

 

, G P

p g h

οƒ… x y xy οƒš x y

x

y

( , )

r r

G P G P P οƒš

 

, G P

 

,

r r

G P

 

, G P

 

,

r r

G P ( )

r

G P G οƒš

slide-39
SLIDE 39

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-40
SLIDE 40

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 3 ARITH 22

slide-41
SLIDE 41

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 3 Conventional

π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 3 π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 3

ARITH 22

slide-42
SLIDE 42

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 3 Conventional

π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 3 π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 3

Adder A Adder B

Mux

2 n

X Y 

2 2

3  

n n

X Y

A

C

B

C

X Y

1

3

2 3 ο€­



n

X Y

RCA ARITH 22

slide-43
SLIDE 43

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 3 Conventional EM Encoding

π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 3 π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 3 π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

3  

n n

X Y

A

C

B

C

X Y

1

3

2 3 ο€­



n

X Y

RCA ARITH 22

slide-44
SLIDE 44

7 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 3 Conventional EM Encoding

π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ 3 π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ 3 π‘Œ + 𝑍 2π‘œβˆ’3 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 3 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

3  

n n

X Y

A

C

B

C

X Y

1

3

2 3 ο€­



n

X Y

n-bit Adder (n,2)-bit Adder

  • ut

C

Y X

n

2

X Y 

n

2 3

X Y

ο€­



RCA RCA ARITH 22

slide-45
SLIDE 45

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-46
SLIDE 46

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization

slide-47
SLIDE 47

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 3 EM Encoding Parallel prefix Adder

slide-48
SLIDE 48

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 3 EM Encoding Parallel prefix Adder

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 pgh pgh pgh pgh pgh

w0 w1 w2 w3 w4 w5 w6 w7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0

s0 s1 s2 s3 s4 s5 s6 s7

1 a

c

2 a

c

3 a

c

4 a

c

5 a

c

6 a

c

7 a

c

a a a a a a a a b b b b b b b b

1 b

c

2 b

c

3 b

c

4 b

c

5 b

c

6 b

c

7 b

c

7:0

Gο‚’

7:0

Gο‚’

7:0

Gο‚’

7:0

G

slide-49
SLIDE 49

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 3 EM Encoding Parallel prefix Adder

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 pgh pgh pgh pgh pgh

w0 w1 w2 w3 w4 w5 w6 w7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0

s0 s1 s2 s3 s4 s5 s6 s7

1 a

c

2 a

c

3 a

c

4 a

c

5 a

c

6 a

c

7 a

c

a a a a a a a a b b b b b b b b

1 b

c

2 b

c

3 b

c

4 b

c

5 b

c

6 b

c

7 b

c

7:0

Gο‚’

7:0

Gο‚’

7:0

Gο‚’

7:0

G

slide-50
SLIDE 50

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 3 EM Encoding Parallel prefix Adder

HA pgh pgh pgh pgh pgh pgβ€²h HA HA HA HA HA HA HA

x0 x1 x2 x3 x4 x5 x6 x7 y0 y1 y2 y3 y4 y5 y6 y7

u1 u2 u3 u4 u5 u6 u7 v1 v2 v3 v4 v5 v6 v7

(g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g 7,p7) (g1,pβ€²

1)

(G2:0,Pβ€²

2:0)

(G3:0,Pβ€²

3:0)

(G4:0,Pβ€²

4:0)

(G5:0,Pβ€²

5:0)

(G6:0,P'

6:0)

G'

7:0

c3 c4 c5 c6

h3

c7

h4 h5 h6 h7

s2 s3 s4 s5 s6 s7

(G1:0,Pβ€²

1:0)

c2 pΒ΄gh

s1

c1

h2 h1 h0

s0

u0 v8

HA p g h

οƒ… x y xy οƒ… u v uv οƒš u v

1 1

οƒ… u v

x

u

1

u y v

1

v

 

, G P   ,

r r

G P   ,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P   ,

r r

G P

 

, G P   , G P

1 1

οƒš οƒš u v u u

1 1

u v

pΒ΄ g h p gΒ΄ h

7

u

7

v

8

v

7 7

οƒ… u v

7 7

οƒš u v

7 7 8

οƒš uv v

slide-51
SLIDE 51

8 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 3 EM Encoding Parallel prefix Adder

HA pgh pgh pgh pgh pgh pgβ€²h HA HA HA HA HA HA HA

x0 x1 x2 x3 x4 x5 x6 x7 y0 y1 y2 y3 y4 y5 y6 y7

u1 u2 u3 u4 u5 u6 u7 v1 v2 v3 v4 v5 v6 v7

(g2,p2) (g3,p3) (g4,p4) (g5,p5) (g6,p6) (g 7,p7) (g1,pβ€²

1)

(G2:0,Pβ€²

2:0)

(G3:0,Pβ€²

3:0)

(G4:0,Pβ€²

4:0)

(G5:0,Pβ€²

5:0)

(G6:0,P'

6:0)

G'

7:0

c3 c4 c5 c6

h3

c7

h4 h5 h6 h7

s2 s3 s4 s5 s6 s7

(G1:0,Pβ€²

1:0)

c2 pΒ΄gh

s1

c1

h2 h1 h0

s0

u0 v8

HA p g h

οƒ… x y xy οƒ… u v uv οƒš u v

1 1

οƒ… u v

x

u

1

u y v

1

v

 

, G P   ,

r r

G P   ,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P   ,

r r

G P

 

, G P   , G P

1 1

οƒš οƒš u v u u

1 1

u v

pΒ΄ g h p gΒ΄ h

7

u

7

v

8

v

7 7

οƒ… u v

7 7

οƒš u v

7 7 8

οƒš uv v

slide-52
SLIDE 52

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-53
SLIDE 53

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 ARITH 22

slide-54
SLIDE 54

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 Conventional

π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ (2π‘Ÿ + 1)

ARITH 22

slide-55
SLIDE 55

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 Conventional

π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ (2π‘Ÿ + 1)

Adder A Adder B

Mux

2 n

X Y 

2 2

2

1

n n

q

X Y  



A

C

B

C

X Y

1

2 1

q 

2 2 1

n q

X Y

ο€­ ο€­



RCA ARITH 22

slide-56
SLIDE 56

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 EM Encoding Conventional

π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

2

1

n n

q

X Y  



A

C

B

C

X Y

1

2 1

q 

2 2 1

n q

X Y

ο€­ ο€­



RCA ARITH 22

slide-57
SLIDE 57

9 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Modulo 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 EM Encoding Conventional

π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ βˆ’ (2π‘Ÿ + 1) π‘Œ + 𝑍 2π‘œβˆ’2qβˆ’1 = π‘Œ + 𝑍, if π‘Œ + 𝑍 < 2π‘œ π‘Œ + 𝑍 + 2q + 1 2π‘œ, if π‘Œ + 𝑍 β‰₯ 2π‘œ

Adder A Adder B

Mux

2 n

X Y 

2 2

2

1

n n

q

X Y  



A

C

B

C

X Y

1

2 1

q 

2 2 1

n q

X Y

ο€­ ο€­



n-bit Adder (n,q+1)-bit Adder

  • ut

C

Y X

n

2

X Y 

n q

2 2 1

X Y

ο€­ ο€­



RCA RCA ARITH 22

slide-58
SLIDE 58

10 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization

slide-59
SLIDE 59

10 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 EM Parallel prefix Adder(π‘œ = 8, π‘Ÿ = 4)

slide-60
SLIDE 60

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 pgh pgh pgh pgh pgh

w0 w1 w2 w3 w4 w5 w6 w7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0

s0 s1 s2 s3 s4 s5 s6 s7

1 a

c

2 a

c

3 a

c

4 a

c

5 a

c

6 a

c

7 a

c

a a a a a a a a b b b b b b b b

1 b

c

2 b

c

3 b

c

4 b

c

5 b

c

6 b

c

7 b

c

7:0

Gο‚’

7:0

Gο‚’

7:0

Gο‚’

7:0

G

10 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 EM Parallel prefix Adder(π‘œ = 8, π‘Ÿ = 4)

slide-61
SLIDE 61

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0 pgh pgh pgh pgh pgh

w0 w1 w2 w3 w4 w5 w6 w7

h3 h4 h5 h6 h7 h2 h1 pgh pgh pgh h0

s0 s1 s2 s3 s4 s5 s6 s7

1 a

c

2 a

c

3 a

c

4 a

c

5 a

c

6 a

c

7 a

c

a a a a a a a a b b b b b b b b

1 b

c

2 b

c

3 b

c

4 b

c

5 b

c

6 b

c

7 b

c

7:0

Gο‚’

7:0

Gο‚’

7:0

Gο‚’

7:0

G

10 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Parallel Prefix Realization Modulo- 2π‘œ βˆ’ 2π‘Ÿ βˆ’ 1 EM Parallel prefix Adder(π‘œ = 8, π‘Ÿ = 4)

slide-62
SLIDE 62

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ

slide-63
SLIDE 63

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ

𝑭𝑩𝑫 =

𝒀 + 𝒁 π±π¨βˆ’πŸ … 𝐱𝐫 … 𝐱𝟐 π’™πŸ 𝒙𝒐

slide-64
SLIDE 64

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ 𝑻 π“π¨βˆ’πŸ … 𝐓𝐫 … π“πŸ π‘»πŸ 𝜺 𝑭𝑩𝑫 𝒙𝒐

𝜺 = 2q + 1

𝒙𝒐

slide-65
SLIDE 65

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ 𝑻 π“π¨βˆ’πŸ … 𝐓𝐫 … π“πŸ π‘»πŸ 𝜺 𝑭𝑩𝑫

(𝑓. 𝑕. π‘œ = 8 π‘Ÿ = 4) 𝜺 = 2q + 1

𝒙𝒐 𝒙𝒐

slide-66
SLIDE 66

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ 𝑻 π“π¨βˆ’πŸ … 𝐓𝐫 … π“πŸ π‘»πŸ 𝜺 𝑭𝑩𝑫 Input Collective value (π‘¦π‘Ÿ, π‘§π‘Ÿ, π‘₯π‘œ, π·π‘Ÿ) π·π‘Ÿ+1 π‘Œ = 10010001 4 2 𝑍 = 10011111

(𝑓. 𝑕. π‘œ = 8 π‘Ÿ = 4) 𝜺 = 2q + 1

𝒙𝒐 𝒙𝒐

slide-67
SLIDE 67

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ 𝑻 π“π¨βˆ’πŸ … 𝐓𝐫 … π“πŸ π‘»πŸ 𝜺 𝑭𝑩𝑫 Input Collective value (π‘¦π‘Ÿ, π‘§π‘Ÿ, π‘₯π‘œ, π·π‘Ÿ) π·π‘Ÿ+1 π‘Œ = 10010001 4 2 𝑍 = 10011111 π‘Œ = 10010000 3 1 𝑍 = 10011110

(𝑓. 𝑕. π‘œ = 8 π‘Ÿ = 4) 𝜺 = 2q + 1

𝒙𝒐 𝒙𝒐

slide-68
SLIDE 68

11 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

𝒀 π’šπ’βˆ’πŸ … π’šπ’“ … π’šπŸ π’šπŸ 𝒁 π’›π’βˆ’πŸ … 𝒛𝒓 … π’›πŸ π’›πŸ 𝑻 π“π¨βˆ’πŸ … 𝐓𝐫 … π“πŸ π‘»πŸ 𝜺 𝑭𝑩𝑫 Input Collective value (π‘¦π‘Ÿ, π‘§π‘Ÿ, π‘₯π‘œ, π·π‘Ÿ) π·π‘Ÿ+1 π‘Œ = 10010001 4 2 𝑍 = 10011111 π‘Œ = 10010000 3 1 𝑍 = 10011110

(𝑓. 𝑕. π‘œ = 8 π‘Ÿ = 4) Problem: Variable -weight carry on position 4 𝜺 = 2q + 1

𝒙𝒐 𝒙𝒐

slide-69
SLIDE 69

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
slide-70
SLIDE 70

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage
slide-71
SLIDE 71

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1

slide-72
SLIDE 72

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀′ 𝒁′ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗

slide-73
SLIDE 73

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀′ 𝒁′ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗

slide-74
SLIDE 74

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗

slide-75
SLIDE 75

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

slide-76
SLIDE 76

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

slide-77
SLIDE 77

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇 π’Šπ¨βˆ’πŸ

β€²

… π’Šπ’“

β€²

π’Šπ«βˆ’πŸ

β€²

… π’ŠπŸ

β€²

π’ŠπŸ

β€²

π’…π’βˆ’πŸ … 𝒅𝒓 π’…π’“βˆ’πŸ … π’…πŸ π’…πŸ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

slide-78
SLIDE 78

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇 π’Šπ¨βˆ’πŸ

β€²

… π’Šπ’“

β€²

π’Šπ«βˆ’πŸ

β€²

… π’ŠπŸ

β€²

π’ŠπŸ

β€²

π’…π’βˆ’πŸ … 𝒅𝒓 π’…π’“βˆ’πŸ … π’…πŸ π’…πŸ 𝑻 π’•π’βˆ’πŸ … 𝒕𝒓 π’•π’“βˆ’πŸ … π’•πŸ π’•πŸ 𝒀 𝒁

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

slide-79
SLIDE 79

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇 π’Šπ¨βˆ’πŸ

β€²

… π’Šπ’“

β€²

π’Šπ«βˆ’πŸ

β€²

… π’ŠπŸ

β€²

π’ŠπŸ

β€²

π’…π’βˆ’πŸ … 𝒅𝒓 π’…π’“βˆ’πŸ … π’…πŸ π’…πŸ 𝑻 π’•π’βˆ’πŸ … 𝒕𝒓 π’•π’“βˆ’πŸ … π’•πŸ π’•πŸ 𝒀 𝒁 𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

slide-80
SLIDE 80

12 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

  • How to solve variable-weight carry problem?
  • Devise a partial carry-save preprocessing stage

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ π’Šπ’βˆ’πŸ … π’Šπ’“ π’‰π’βˆ’πŸ π’‰π’βˆ’πŸ‘ … 𝒀′ 𝒁′ 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇 π’Šπ¨βˆ’πŸ

β€²

… π’Šπ’“

β€²

π’Šπ«βˆ’πŸ

β€²

… π’ŠπŸ

β€²

π’ŠπŸ

β€²

π’…π’βˆ’πŸ … 𝒅𝒓 π’…π’“βˆ’πŸ … π’…πŸ π’…πŸ 𝑻 π’•π’βˆ’πŸ … 𝒕𝒓 π’•π’“βˆ’πŸ … π’•πŸ π’•πŸ 𝒀 𝒁 𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1

Problem: Carry-save Stage is on the critical delay path

π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 β„Žπ‘— = 𝑦𝑗⨁𝑧𝑗 𝑕𝑗 = 𝑦𝑗𝑧𝑗 𝑓 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

slide-81
SLIDE 81

IWSSIP 2014

81 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

slide-82
SLIDE 82

IWSSIP 2014

82 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?
slide-83
SLIDE 83

IWSSIP 2014

83 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

(𝐻, 𝑄) (𝐻′, 𝑄′)

slide-84
SLIDE 84

IWSSIP 2014

84 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

(𝑯𝒋:π’Œ+𝟐

β€²

, 𝑸𝒋:π’Œ+𝟐

β€²

π’Šπ’Œ) = (π’Šπ’‹π‘―π’‹βˆ’πŸ:π’Œ, 𝑰𝒋:π’Œ) π’Œ β‰₯ 𝒓

(𝐻, 𝑄) (𝐻′, 𝑄′)

slide-85
SLIDE 85

IWSSIP 2014

85 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1 (𝑯𝒋:π’Œ+𝟐

β€²

, 𝑸𝒋:π’Œ+𝟐

β€²

π’Šπ’Œ) = (π’Šπ’‹π‘―π’‹βˆ’πŸ:π’Œ, 𝑰𝒋:π’Œ) π’Œ β‰₯ 𝒓

(𝐻, 𝑄) (𝐻′, 𝑄′)

slide-86
SLIDE 86

IWSSIP 2014

86 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1 (𝑯𝒋:π’Œ+𝟐

β€²

, 𝑸𝒋:π’Œ+𝟐

β€²

π’Šπ’Œ) = (π’Šπ’‹π‘―π’‹βˆ’πŸ:π’Œ, 𝑰𝒋:π’Œ) π’Œ β‰₯ 𝒓

(𝐻, 𝑄) (𝐻′, 𝑄′)

slide-87
SLIDE 87

IWSSIP 2014

87 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1 𝑑𝑗 = π»π‘œβˆ’1:0, if 𝑗 = 0 π»π‘—βˆ’1:0 ∨ π‘„π‘—βˆ’1:0π»π‘œβˆ’1:0, if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿπ»π‘Ÿβˆ’1:0 ∨ 𝑄

π‘Ÿ:0 β€²β€² π»π‘œβˆ’1:0,

if 𝑗 = π‘Ÿ + 1 β„Žπ‘—βˆ’1π»π‘—βˆ’2:0 ∨ π‘„π‘—βˆ’1:0

β€²β€²

π»π‘œβˆ’1:0, if 𝑗 > π‘Ÿ + 1 (𝑯𝒋:π’Œ+𝟐

β€²

, 𝑸𝒋:π’Œ+𝟐

β€²

π’Šπ’Œ) = (π’Šπ’‹π‘―π’‹βˆ’πŸ:π’Œ, 𝑰𝒋:π’Œ) π’Œ β‰₯ 𝒓 π‘„π‘Ÿ:0

β€²β€² = β„Žπ‘Ÿ ∨ π‘„π‘Ÿβˆ’1:0 ∨ π»π‘Ÿβˆ’1:0

π‘„π‘—βˆ’1:0

β€²β€²

= π‘„β€²π‘—βˆ’1:π‘Ÿ+1𝑄

π‘Ÿ:0 β€²β€²

(𝐻, 𝑄) (𝐻′, 𝑄′)

slide-88
SLIDE 88

IWSSIP 2014

88 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

13

  • How to solve Carry Save Stage Delay problem?

π’šπ’βˆ’πŸ … π’šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ π’›π’βˆ’πŸ … 𝒛𝒓 π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝒀 𝒁 𝒀′ π’Šπ’βˆ’πŸ … π’Šπ’“ π’šπ’“βˆ’πŸ … π’šπŸ π’šπŸ 𝒁′′ π’‰π’βˆ’πŸ‘ … π’›π’“βˆ’πŸ … π’›πŸ π’›πŸ 𝜺 𝑭𝑩𝑫 𝒇 𝒇

  • Finding a relative between the 𝐻, 𝑄 of π‘Œ + 𝑍 2π‘œβˆ’2π‘Ÿβˆ’1 and 𝐻′, 𝑄′ of π‘Œβ€² + 𝑍′′ 2π‘œβˆ’2π‘Ÿβˆ’1

𝑑𝑗 = π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

, if 𝑗 = 0 π»π‘—βˆ’1:0

β€²

∨ 𝑄

π‘—βˆ’1:0 β€²

(π‘•π‘œβˆ’1 ∨ π»π‘œβˆ’1:0

β€²

), if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿ ∨ 𝑓 π‘‘π‘Ÿ ∨ β„Žπ‘Ÿπ‘“, if 𝑗 = π‘Ÿ + 1 π»π‘—βˆ’1:π‘Ÿ+1

β€²

∨ π‘„π‘—βˆ’1:π‘Ÿ+1

β€²

π‘‘π‘Ÿ+1, if 𝑗 > π‘Ÿ + 1 𝑑𝑗 = π»π‘œβˆ’1:0, if 𝑗 = 0 π»π‘—βˆ’1:0 ∨ π‘„π‘—βˆ’1:0π»π‘œβˆ’1:0, if 1 ≀ 𝑗 ≀ π‘Ÿ β„Žπ‘Ÿπ»π‘Ÿβˆ’1:0 ∨ 𝑄

π‘Ÿ:0 β€²β€² π»π‘œβˆ’1:0,

if 𝑗 = π‘Ÿ + 1 β„Žπ‘—βˆ’1π»π‘—βˆ’2:0 ∨ π‘„π‘—βˆ’1:0

β€²β€²

π»π‘œβˆ’1:0, if 𝑗 > π‘Ÿ + 1 (𝑯𝒋:π’Œ+𝟐

β€²

, 𝑸𝒋:π’Œ+𝟐

β€²

π’Šπ’Œ) = (π’Šπ’‹π‘―π’‹βˆ’πŸ:π’Œ, 𝑰𝒋:π’Œ) π’Œ β‰₯ 𝒓 π‘„π‘Ÿ:0

β€²β€² = β„Žπ‘Ÿ ∨ π‘„π‘Ÿβˆ’1:0 ∨ π»π‘Ÿβˆ’1:0

π‘„π‘—βˆ’1:0

β€²β€²

= π‘„β€²π‘—βˆ’1:π‘Ÿ+1𝑄

π‘Ÿ:0 β€²β€²

(𝐻, 𝑄) (𝐻′, 𝑄′)

The carry-save stage is effectively off the critical delay path

slide-89
SLIDE 89

14 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-90
SLIDE 90

14 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

pghpβ€²hβ€²

pgh pgh pgh

pghpβ€²hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh pghhβ€²

x7 y7

(g0,p0) h6 h5

G7:0

(g7,p7)

y4x4 y5x5 y6 x6

P3:0 G3:0 β„Ž7

β€²

β„Ž6

β€²

β„Ž5

β€²

β„Ž4 β„Ž4 β„Ž0 β„Ž1 β„Ž3 β„Ž2

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏,π‘ΈπŸ’:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ“:𝟏

β€²β€² )

(π‘―πŸ“:𝟏,π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

Eqn.8

π‘ž5

β€²

π‘ž6

β€² π‘ž6

β€²

π‘žβ€² π‘ž5

β€²

π‘ΈπŸ“:𝟏

β€²β€²

π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

p g h hβ€²

 

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒš

i i

x y

i i

x y οƒš

i

x

i

y

p g h 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

p g h p’ hβ€²

i i

x y

i i

x y οƒš 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

i

y

i

x

 

, G P

  ,

r r

G P

 

,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P 

 ,

r r

G P

4

h

5

ο‚’ p

6

ο‚’ p

3:0

P

3:0

G

4:0

ο‚’ο‚’ P

5:0

ο‚’ο‚’ P

6:0

ο‚’ο‚’ P

 

, G P   ,

r r

G P

 

i r

h G P G οƒš

i

h

Eqn.8

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

i

x

i

y

i i

x y οƒš

i i

x y

i i

x y οƒ…  

, G P

 

, G P

Modulo (28βˆ’24 βˆ’ 1)

slide-91
SLIDE 91

14 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

pghpβ€²hβ€²

pgh pgh pgh

pghpβ€²hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh pghhβ€²

x7 y7

(g0,p0) h6 h5

G7:0

(g7,p7)

y4x4 y5x5 y6 x6

P3:0 G3:0 β„Ž7

β€²

β„Ž6

β€²

β„Ž5

β€²

β„Ž4 β„Ž4 β„Ž0 β„Ž1 β„Ž3 β„Ž2

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏,π‘ΈπŸ’:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ“:𝟏

β€²β€² )

(π‘―πŸ“:𝟏,π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

Eqn.8

π‘ž5

β€²

π‘ž6

β€² π‘ž6

β€²

π‘žβ€² π‘ž5

β€²

π‘ΈπŸ“:𝟏

β€²β€²

π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

p g h hβ€²

 

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒš

i i

x y

i i

x y οƒš

i

x

i

y

p g h 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

p g h p’ hβ€²

i i

x y

i i

x y οƒš 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

i

y

i

x

 

, G P

  ,

r r

G P

 

,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P 

 ,

r r

G P

4

h

5

ο‚’ p

6

ο‚’ p

3:0

P

3:0

G

4:0

ο‚’ο‚’ P

5:0

ο‚’ο‚’ P

6:0

ο‚’ο‚’ P

 

, G P   ,

r r

G P

 

i r

h G P G οƒš

i

h

Eqn.8

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

i

x

i

y

i i

x y οƒš

i i

x y

i i

x y οƒ…  

, G P

 

, G P

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

c3 c4 c5 c6 h3 c7 h4 h5 h6 h7 h2 c2 c1 h1 pgh pgh pgh h0

G7:0

(G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0)(G1:0,P1:0) (G0:0,P0:0)

s0 s1 s2 s3 s4 s5 s6 s7

p g h

οƒ… x y xy οƒš x y

x

y  

, G P

 

,

r r

G P

 

, οƒš

r r

G P G P P οƒš

r

G P G

 

, G P

 

,

r r

G P

 

, G P

 

, G P

Modulo (28βˆ’24 βˆ’ 1) Modulo (28βˆ’1)

slide-92
SLIDE 92

14 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

pghpβ€²hβ€²

pgh pgh pgh

pghpβ€²hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh pghhβ€²

x7 y7

(g0,p0) h6 h5

G7:0

(g7,p7)

y4x4 y5x5 y6 x6

P3:0 G3:0 β„Ž7

β€²

β„Ž6

β€²

β„Ž5

β€²

β„Ž4 β„Ž4 β„Ž0 β„Ž1 β„Ž3 β„Ž2

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏,π‘ΈπŸ’:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ“:𝟏

β€²β€² )

(π‘―πŸ“:𝟏,π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

Eqn.8

π‘ž5

β€²

π‘ž6

β€² π‘ž6

β€²

π‘žβ€² π‘ž5

β€²

π‘ΈπŸ“:𝟏

β€²β€²

π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

pgh pgh pgh pgh pgh

y0 y1 y2 y3 y4 y5 y6 y7 x0 x1 x2 x3 x4 x5 x6 x7

c3 c4 c5 c6 h3 c7 h4 h5 h6 h7 h2 c2 c1 h1 pgh pgh pgh h0

G7:0

(G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0)(G1:0,P1:0) (G0:0,P0:0)

s0 s1 s2 s3 s4 s5 s6 s7

Modulo (28βˆ’24 βˆ’ 1) Modulo (28βˆ’1)

Problem : for 𝒓 > 𝒐/πŸ‘ the critical delay path is one βˆ†π‘― more than other case

slide-93
SLIDE 93

15

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue 15

ARITH 22

slide-94
SLIDE 94

15

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

  • How to solve extra delay critical problem for π‘Ÿ >

π‘œ 2 problem?

15

ARITH 22

slide-95
SLIDE 95

15

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

  • How to solve extra delay critical problem for π‘Ÿ >

π‘œ 2 problem?

  • Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use

KS architecture and the bottom level use LF )

pgh pgh pgh pgh

pghp hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh

pghhβ€²

x7 y7

(g0,p0)

h6

G7:0

(g7,p7)

y5x5 y6 x6

p4 g4

β„Ž0 β„Ž1 β„Ž2 β„Ž3 β„Ž4 β„Ž5 β„Ž6

β€²

β„Ž7

β€²

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ’:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ“:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

π‘―πŸ’:𝟏 ∨ π‘ΈπŸ’:𝟏 π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π’’πŸ

Eqn.9

β„Ž5 π‘ž6

β€² π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

𝐻3:0⋁𝑄3:0

π‘ž6

β€²

p g h hβ€²

 

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒš

i i

x y

i i

x y οƒš

i

x

i

y

p g h

1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

p g h p’ hβ€²

i i

x y

i i

x y οƒš 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

i

y

i

x

 

, G P

  ,

r r

G P

 

,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P 

 ,

r r

G P

 

, G P   ,

r r

G P  

i r

h G P G οƒš

i

h

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

i

x

i

y

i i

x y οƒš

i i

x y

i i

x y οƒ…  

, G P

 

, G P

5

h

6

ο‚’ p

4

P

5:0

ο‚’ο‚’ P

6:0

ο‚’ο‚’ P

Eqn.9

 

, G P   ,

r r

G P ( )

r r

G P G P οƒš οƒš οƒš

r

G P G

οƒš

r r

G P

4

g

3:0 3:0

οƒš G P

15

ARITH 22

slide-96
SLIDE 96

15

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

  • How to solve extra delay critical problem for π‘Ÿ >

π‘œ 2 problem?

  • Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use

KS architecture and the bottom level use LF )

pgh pgh pgh pgh

pghp hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh

pghhβ€²

x7 y7

(g0,p0)

h6

G7:0

(g7,p7)

y5x5 y6 x6

p4 g4

β„Ž0 β„Ž1 β„Ž2 β„Ž3 β„Ž4 β„Ž5 β„Ž6

β€²

β„Ž7

β€²

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ’:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ“:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

π‘―πŸ’:𝟏 ∨ π‘ΈπŸ’:𝟏 π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π’’πŸ

Eqn.9

β„Ž5 π‘ž6

β€² π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

𝐻3:0⋁𝑄3:0

π‘ž6

β€²

p g h hβ€²

 

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒš

i i

x y

i i

x y οƒš

i

x

i

y

p g h

1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

p g h p’ hβ€²

i i

x y

i i

x y οƒš 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

i

y

i

x

 

, G P

  ,

r r

G P

 

,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P 

 ,

r r

G P

 

, G P   ,

r r

G P  

i r

h G P G οƒš

i

h

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

i

x

i

y

i i

x y οƒš

i i

x y

i i

x y οƒ…  

, G P

 

, G P

5

h

6

ο‚’ p

4

P

5:0

ο‚’ο‚’ P

6:0

ο‚’ο‚’ P

Eqn.9

 

, G P   ,

r r

G P ( )

r r

G P G P οƒš οƒš οƒš

r

G P G

οƒš

r r

G P

4

g

3:0 3:0

οƒš G P

KS LF

15

ARITH 22

slide-97
SLIDE 97

15

Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

  • How to solve extra delay critical problem for π‘Ÿ >

π‘œ 2 problem?

  • Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use

KS architecture and the bottom level use LF )

pgh pgh pgh pgh

pghp hβ€²

x0 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6

(g2,p2) (g3,p3) (g5,p4) (g5,p5) (g6,p6) (g1,p1)

c3 c4 c5 c6 c7

s2 s3 s4 s5 s6 s7

c2 pgh

s1

c1

s0

pgh

pghhβ€²

x7 y7

(g0,p0)

h6

G7:0

(g7,p7)

y5x5 y6 x6

p4 g4

β„Ž0 β„Ž1 β„Ž2 β„Ž3 β„Ž4 β„Ž5 β„Ž6

β€²

β„Ž7

β€²

(π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ:𝟏, π‘ΈπŸ:𝟏) (π‘―πŸ‘:𝟏, π‘ΈπŸ‘:𝟏) (π‘―πŸ’:𝟏, π‘ΈπŸ’:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ“:𝟏) (π‘―πŸ“:𝟏, π‘ΈπŸ”:𝟏

β€²β€² )

(π‘―πŸ”:𝟏, π‘ΈπŸ•:𝟏

β€²β€² )

π‘―πŸ’:𝟏 ∨ π‘ΈπŸ’:𝟏 π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π‘―πŸ:𝟏 ∨ π‘ΈπŸ:𝟏

π’’πŸ

Eqn.9

β„Ž5 π‘ž6

β€² π‘ΈπŸ”:𝟏

β€²β€²

π‘ΈπŸ•:𝟏

β€²β€²

𝐻3:0⋁𝑄3:0

π‘ž6

β€²

p g h hβ€²

 

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒš

i i

x y

i i

x y οƒš

i

x

i

y

p g h

1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

p g h p’ hβ€²

i i

x y

i i

x y οƒš 1 i

x ο€­

1 i

y ο€­

i i

x y οƒ…

i

y

i

x

 

, G P

  ,

r r

G P

 

,

r r

G P G P P οƒš

r

G P G οƒš

 

, G P 

 ,

r r

G P

 

, G P   ,

r r

G P  

i r

h G P G οƒš

i

h

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

1 1 i i i i

x y x y

ο€­ ο€­

οƒ… οƒ…

i

x

i

y

i i

x y οƒš

i i

x y

i i

x y οƒ…  

, G P

 

, G P

5

h

6

ο‚’ p

4

P

5:0

ο‚’ο‚’ P

6:0

ο‚’ο‚’ P

Eqn.9

 

, G P   ,

r r

G P ( )

r r

G P G P οƒš οƒš οƒš

r

G P G

οƒš

r r

G P

4

g

3:0 3:0

οƒš G P

  • Using twin nodes (Computing 𝐻𝑗:0 and 𝐻𝑗:0 ∨ 𝑄𝑗:0 as a same time)

15

ARITH 22

slide-98
SLIDE 98

16 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-99
SLIDE 99

16 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Design Delay (βˆ†π‘―) Area (𝓑𝑯) [4] 4 log π‘œ + 8 6π‘œ log π‘œ + 5π‘œ + 1 [5] 4 log π‘œ + 12 3π‘œ log π‘œ + 10π‘œ + 1 [6] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ βˆ’ 1 log π‘œ + 3 π‘œ βˆ’ 1 log π‘œ βˆ’ 1 + 5π‘œ + 1 [7] 2 log π‘œ βˆ’ 1 + 2 log (π‘œ βˆ’ 2) + 8 3 π‘œ βˆ’ 2 log π‘œ βˆ’ 2 βˆ’ log (π‘œ βˆ’ 1) + 7π‘œ + 27 [8] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ log (π‘œ βˆ’ 1) + 13π‘œ βˆ’ 5 [9] 2 log π‘œ + 7 3π‘œ βˆ’ 1 log π‘œ + 11.5π‘œ + 1 [10] 2 log π‘œ + 7 3π‘œ log π‘œ + 6π‘œ βˆ’ 3π‘Ÿ + 2 + 𝒝𝑑 [11] (𝒓 = 𝒐 βˆ’ πŸ‘) 2 log π‘œ + 5 3π‘œ log π‘œ + 1.5π‘œ log π‘œ βˆ’ 1 + 7π‘œ + 2 log π‘œβˆ’1 βˆ’1 [13]-RPP (𝒓 = 𝟐) 2 log (π‘œ βˆ’ 1) + 6 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 New (𝒓 ≀ 𝒐/πŸ‘) 2 log π‘œ + 5 3 π‘œ βˆ’ 1 log π‘œ + 7π‘œ βˆ’ 3π‘Ÿ βˆ’ 1 + 𝒝𝑄′′ New (𝒓 > 𝒐/πŸ‘) 2 log π‘œ + 5 3(π‘œ βˆ’ 1) log π‘œ + 5.5π‘œ βˆ’ 3π‘Ÿ + 2 log π‘œ + 𝒝𝑄′′ [3]-RPP 2 log π‘œ + 5 3π‘œ log π‘œ + 4π‘œ

βˆ†π‘―: Delay of Simple Gate 𝓑𝑯: Area of Simple Gate

Analytical gate Level Evaluation

ARITH 22

slide-100
SLIDE 100

16 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Design Delay (βˆ†π‘―) Area (𝓑𝑯) [4] 4 log π‘œ + 8 6π‘œ log π‘œ + 5π‘œ + 1 [5] 4 log π‘œ + 12 3π‘œ log π‘œ + 10π‘œ + 1 [6] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ βˆ’ 1 log π‘œ + 3 π‘œ βˆ’ 1 log π‘œ βˆ’ 1 + 5π‘œ + 1 [7] 2 log π‘œ βˆ’ 1 + 2 log (π‘œ βˆ’ 2) + 8 3 π‘œ βˆ’ 2 log π‘œ βˆ’ 2 βˆ’ log (π‘œ βˆ’ 1) + 7π‘œ + 27 [8] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ log (π‘œ βˆ’ 1) + 13π‘œ βˆ’ 5 [9] 2 log π‘œ + 7 3π‘œ βˆ’ 1 log π‘œ + 11.5π‘œ + 1 [10] 2 log π‘œ + 7 3π‘œ log π‘œ + 6π‘œ βˆ’ 3π‘Ÿ + 2 + 𝒝𝑑 [11] (𝒓 = 𝒐 βˆ’ πŸ‘) 2 log π‘œ + 5 3π‘œ log π‘œ + 1.5π‘œ log π‘œ βˆ’ 1 + 7π‘œ + 2 log π‘œβˆ’1 βˆ’1 [13]-RPP (𝒓 = 𝟐) 2 log (π‘œ βˆ’ 1) + 6 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 New (𝒓 ≀ 𝒐/πŸ‘) 2 log π‘œ + 5 3 π‘œ βˆ’ 1 log π‘œ + 7π‘œ βˆ’ 3π‘Ÿ βˆ’ 1 + 𝒝𝑄′′ New (𝒓 > 𝒐/πŸ‘) 2 log π‘œ + 5 3(π‘œ βˆ’ 1) log π‘œ + 5.5π‘œ βˆ’ 3π‘Ÿ + 2 log π‘œ + 𝒝𝑄′′ [3]-RPP 2 log π‘œ + 5 3π‘œ log π‘œ + 4π‘œ

βˆ†π‘―: Delay of Simple Gate 𝓑𝑯: Area of Simple Gate

Analytical gate Level Evaluation

ARITH 22

slide-101
SLIDE 101

16 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

Design Delay (βˆ†π‘―) Area (𝓑𝑯) [4] 4 log π‘œ + 8 6π‘œ log π‘œ + 5π‘œ + 1 [5] 4 log π‘œ + 12 3π‘œ log π‘œ + 10π‘œ + 1 [6] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ βˆ’ 1 log π‘œ + 3 π‘œ βˆ’ 1 log π‘œ βˆ’ 1 + 5π‘œ + 1 [7] 2 log π‘œ βˆ’ 1 + 2 log (π‘œ βˆ’ 2) + 8 3 π‘œ βˆ’ 2 log π‘œ βˆ’ 2 βˆ’ log (π‘œ βˆ’ 1) + 7π‘œ + 27 [8] 2 log (π‘œ βˆ’ 1) + 7 3 π‘œ log (π‘œ βˆ’ 1) + 13π‘œ βˆ’ 5 [9] 2 log π‘œ + 7 3π‘œ βˆ’ 1 log π‘œ + 11.5π‘œ + 1 [10] 2 log π‘œ + 7 3π‘œ log π‘œ + 6π‘œ βˆ’ 3π‘Ÿ + 2 + 𝒝𝑑 [11] (𝒓 = 𝒐 βˆ’ πŸ‘) 2 log π‘œ + 5 3π‘œ log π‘œ + 1.5π‘œ log π‘œ βˆ’ 1 + 7π‘œ + 2 log π‘œβˆ’1 βˆ’1 [13]-RPP (𝒓 = 𝟐) 2 log (π‘œ βˆ’ 1) + 6 3 π‘œ βˆ’ 1 log(π‘œ βˆ’ 1) + 8π‘œ βˆ’ 1 New (𝒓 ≀ 𝒐/πŸ‘) 2 log π‘œ + 5 3 π‘œ βˆ’ 1 log π‘œ + 7π‘œ βˆ’ 3π‘Ÿ βˆ’ 1 + 𝒝𝑄′′ New (𝒓 > 𝒐/πŸ‘) 2 log π‘œ + 5 3(π‘œ βˆ’ 1) log π‘œ + 5.5π‘œ βˆ’ 3π‘Ÿ + 2 log π‘œ + 𝒝𝑄′′ [3]-RPP 2 log π‘œ + 5 3π‘œ log π‘œ + 4π‘œ

βˆ†π‘―: Delay of Simple Gate 𝓑𝑯: Area of Simple Gate

Analytical gate Level Evaluation

ARITH 22

slide-102
SLIDE 102

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-103
SLIDE 103

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Synthesis: Synopsys Design Compiler Technology file: 130 nm

slide-104
SLIDE 104

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Synthesis: Synopsys Design Compiler Technology file: 130 nm

π‘Ÿ 1 2 3 4 5 6 Least delay (𝒐𝒕) 0.71 0.71 0.72 0.71 0.70 0.70 Area (π‚π’πŸ‘) 1405 1268 1224 1129 1110 910 Power (𝝂𝒙) 449 408 383 353 326 264

Performance measures of the New design (π‘œ = 8, 1 ≀ π‘Ÿ ≀ 6)

slide-105
SLIDE 105

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Design Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.77 1.08 1828 1.30 1.41 577 1.28 1.39 [8] 0.84 1.18 1501 1.07 1.26 499 1.11 1.31 [9] 0.83 1.17 1524 1.08 1.27 500 1.11 1.30 [10] 0.84 1.18 1504 1.07 1.27 500 1.11 1.32 [13] 0.80 1.12 1400 1.00 1.12 446 0.99 1.12 New 0.71 1.00 1405 1.00 1.00 449 1.00 1.00

Synthesis: Synopsys Design Compiler Technology file: 130 nm (n=8,q=1)

slide-106
SLIDE 106

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Design Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.77 1.08 1828 1.30 1.41 577 1.28 1.39 [8] 0.84 1.18 1501 1.07 1.26 499 1.11 1.31 [9] 0.83 1.17 1524 1.08 1.27 500 1.11 1.30 [10] 0.84 1.18 1504 1.07 1.27 500 1.11 1.32 [13] 0.80 1.12 1400 1.00 1.12 446 0.99 1.12 New 0.71 1.00 1405 1.00 1.00 449 1.00 1.00

Synthesis: Synopsys Design Compiler Technology file: 130 nm (n=8,q=6) (n=8,q=1)

Design Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.77 1.10 1825 2.00 2.21 550 2.08 2.29 [8] 0.84 1.20 1404 1.54 1.85 434 1.64 1.97 [9] 0.88 1.26 1338 1.47 1.85 454 1.72 2.16 [10] 0.75 1.07 1480 1.63 1.74 452 1.71 1.83 [11] 0.73 1.04 1394 1.53 1.60 442 1.67 1.75 New 0.70 1.00 910 1.00 1.00 264 1.00 1.00

slide-107
SLIDE 107

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Synthesis: Synopsys Design Compiler Technology file: 130 nm

Desig n Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.88 1.03 4589 1.41 1.46 1383 1.40 1.44 [8] 0.90 1.06 3725 1.15 1.21 1190 1.20 1.27 [9] 0.92 1.08 3828 1.18 1.28 1295 1.31 1.41 [10] 0.97 1.14 3394 1.04 1.19 1075 1.08 1.24 [13] 0.89 1.05 3414 1.05 1.10 1018 1.03 1.08 New 0.85 1.00 3248 1.00 1.00 991 1.00 1.00

(n=16,q=1)

slide-108
SLIDE 108

17 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22 Synthesis: Synopsys Design Compiler Technology file: 130 nm

Desig n Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.88 1.03 4589 1.41 1.46 1383 1.40 1.44 [8] 0.90 1.06 3725 1.15 1.21 1190 1.20 1.27 [9] 0.92 1.08 3828 1.18 1.28 1295 1.31 1.41 [10] 0.97 1.14 3394 1.04 1.19 1075 1.08 1.24 [13] 0.89 1.05 3414 1.05 1.10 1018 1.03 1.08 New 0.85 1.00 3248 1.00 1.00 991 1.00 1.00 Desig n Least delay (𝒐𝒕) Ratio Area (π‚π’πŸ‘) Ratio AT Power 𝝂𝒙 Ratio PDP [6] 0.90 1.06 4538 2.18 2.31 1360 2.34 2.48 [8] 0.91 1.07 3988 1.91 2.05 1262 2.17 2.32 [9] 0.90 1.06 3855 1.85 1.96 1341 2.31 2.44 [10] 0.89 1.05 3394 1.63 1.71 940 1.62 1.69 [11] 0.87 1.02 3829 1.84 1.88 1226 2.11 2.16 New 0.85 1.00 2083 1.00 1.00 581 1.00 1.00

(n=16,q=1) (n=16,q=14)

slide-109
SLIDE 109

18 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

slide-110
SLIDE 110

18 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Conclusion

  • Design and implement a new Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 parallel prefix adder

based on only one interim sum which has the same delay complexity as the modulo- πŸ‘π’ βˆ’ 𝟐 adder .

slide-111
SLIDE 111

18 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Conclusion

  • Design and implement a new Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 parallel prefix adder

based on only one interim sum which has the same delay complexity as the modulo- πŸ‘π’ βˆ’ 𝟐 adder .

  • Future work
slide-112
SLIDE 112

18 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22

Conclusion

  • Design and implement a new Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 parallel prefix adder

based on only one interim sum which has the same delay complexity as the modulo- πŸ‘π’ βˆ’ 𝟐 adder .

  • Future work
  • Design and implement Modulo-(πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐) multiplier
slide-113
SLIDE 113

Questions

19 Modulo- πŸ‘π’ βˆ’ πŸ‘π’“ βˆ’ 𝟐 Parallel Prefix Addition via Excess-Modulo Encoding of Residue

ARITH 22