Modeling Testing Evaluating 100 c c 90 Network latency - - PowerPoint PPT Presentation

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Modeling Testing Evaluating 100 c c 90 Network latency - - PowerPoint PPT Presentation

Sep 28, 2023 355 likes •565 views

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Modeling Testing Evaluating 100 c c 90 Network latency (cycles) 80 Input c c Expect? 70 R 60 c c 50 40 c c 30 20 10 Functional-Level Unit 0

slide-1
SLIDE 1

1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 Energy (pJ/pkt) Number of Router Ports

Cheng Tan Cornell University 1/20

Evaluating Testing

R R R R R R R R

Unit

R

Expect? Input Input

=?

10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 Network latency (cycles) Injection rate

Characterization Simulation

Modeling

Property-Based Random Functional-Level Cycle-Level Physical-Level Register-Transfer-Level PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Generation

c c c c c c c c

Integration Expect? Input

C C C C C C C C r r r r r r r r C C C C C C C C r r r r r r r r c c c c c c c c C C C C C C C C r r r r r r r r

slide-2
SLIDE 2

Cheng Tan Cornell University 2/20

Lang.

Evaluating

Config.Function- Level Cycle- Level RTL Physical- Level Unit Int. Sim. RTL Gen. ASIC Char.

Modeling Testing

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

BookSim2 C++ Garnet Noxim C++ SysC Connect Netmaker OpenSMART OpenSoC BSV

Verilog Chisel Chisel

DSENT Orion2 COSI

C++ C++ C++

PyOCN

PyMTL Property- based

slide-3
SLIDE 3

Overview of PyOCN Framework

Cheng Tan Cornell University 3/20

OCN Config. FL model CL model RTL model PL model SoC Simulator Network Lib. Channel Lib. Router Lib. InputUnit Lib. RouteUnit Lib. SwitchUnit Lib. OutputUnit Lib. PyOCN

  • Std. Lib

EDA toolflow CL Perf. stats RTL Perf. stats AET stats Floor- plan Verilog

Characterizing Generating

Testing Modeling Evaluating

Simulating

Param. System PyMTL Elaborate Test Harness PyMTL

  • Sim. Pass

PyMTL

  • Sim. Pass

PyMTL

  • Sim. Pass

PBRT Tester Integration Tester Unit Tester PyMTL

  • Gen. Pass

PyOCN EDA script PyMTL

  • Place. Pass

PyOCN Simulator

  • Enables multi-level modeling to facilitate rapid design-space exploration
  • Provides test harnesses for testing OCN designs modeled at different abstraction levels
  • Can simulate OCNs at various abstraction levels, generate synthesizable Verilog, and drive a

commercial standard-cell-based toolflow for characterizing OCN area, energy, and timing

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

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SLIDE 4

1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 Energy (pJ/pkt) Number of Router Ports

Cheng Tan Cornell University 4/20

Evaluating Testing

R R R R R R R R

Unit

R

Expect? Input Input

=?

10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 Network latency (cycles) Injection rate

Characterization Simulation

Modeling

Property-Based Random Function-Level Cycle-Level Physical-Level Register-Transfer-Level PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Generation

c c c c c c c c

Integration Expect? Input

C C C C C C C C r r r r r r r r C C C C C C C C r r r r r r r r c c c c c c c c C C C C C C C C r r r r r r r r

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SLIDE 5

Cheng Tan Cornell University 5/20

PyOCN for Modeling OCNs

written in Python

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

. . . . . . . . . Channel Input Unit Output Unit Channel Input Unit Output Unit Channel Input Unit Output Unit Switch Unit Switch Unit Switch Unit Route Unit Route Unit Route Unit

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SLIDE 6

Cheng Tan Cornell University 6/20

Function-Level Modeling

FL Implementation of Ring Network Python function

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

slide-7
SLIDE 7
  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

Cheng Tan Cornell University 7/20

Cycle-Level Modeling

CL Implementation of Switch Unit

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

slide-8
SLIDE 8
  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

Cheng Tan Cornell University 8/20

RTL Implementation of Switch Unit

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

Register-Transfer-Level Modeling

slide-9
SLIDE 9
  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

Cheng Tan Cornell University 9/20

Physical-Level Modeling

PL Implementation of Ring Network

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

slide-10
SLIDE 10
  • New Modular Router Microarchitecture

– Single unified router microarchitecture for all networks – Easily configure different units for different topologies, routing algorithms, and arbitration algorithms – Users can also provide their own units

  • Multi-level modeling

– Functional-Level – Cycle-Level – Register-Transfer-Level – Physical-Level

Cheng Tan Cornell University 10/20

PyOCN for Modeling OCNs

Multi-level simulation speedup and accuracy

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Injection Rate Speedup Accuracy

0.01 17.9X 86% 0.1 15.5X 87% 0.2 14.2X 87% 0.3 13.3X 97% 0.4 13.0X 74%

slide-11
SLIDE 11

1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 Energy (pJ/pkt) Number of Router Ports

Cheng Tan Cornell University 11/20

Evaluating Testing

R R R R R R R R

Unit

R

Expect? Input Input

=?

10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 Network latency (cycles) Injection rate

Characterization Simulation

Modeling

Property-Based Random Function-Level Cycle-Level Physical-Level Register-Transfer-Level PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Generation

c c c c c c c c

Integration Expect? Input

C C C C C C C C r r r r r r r r C C C C C C C C r r r r r r r r c c c c c c c c C C C C C C C C r r r r r r r r

slide-12
SLIDE 12

Cheng Tan Cornell University 12/20

Unit and Integration Test

PyOCN provides extensive test suites to unit test the basic network components. PyOCN also enables integration test on complete network instances.

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

R

Expect? Input

C C C C C C C C r r r r r r r r

Expect?

Input

slide-13
SLIDE 13

Cheng Tan Cornell University 13/20

Property-Based Random Test

PyOCN uses a type-based random data generator for all inputs and checking if the DUT violates the given specification.

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Input

=?

c c c c c c c c C C C C C C C C r r r r r r r r

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SLIDE 14

1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 Energy (pJ/pkt) Number of Router Ports

Cheng Tan Cornell University 14/20

Evaluating Testing

R R R R R R R R

Unit

R

Expect? Input Input

=?

10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 Network latency (cycles) Injection rate

Characterization Simulation

Modeling

Property-Based Random Function-Level Cycle-Level Physical-Level Register-Transfer-Level PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks Generation

c c c c c c c c

Integration Expect? Input

C C C C C C C C r r r r r r r r C C C C C C C C r r r r r r r r c c c c c c c c C C C C C C C C r r r r r r r r

slide-15
SLIDE 15

Cheng Tan Cornell University 15/20

PyOCN for Evaluating OCNs

0.1 0.2 0.3 0.4 0.5 0.6 ring bfly mesh cmesh torus 0.1 0.2 0.3 0.4 0.5 0.6 0.1 0.2 0.3 0.4 0.5 0.6 10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 Network latency (cycles)

random partition neighbor complement

Injection rate

4000 8000 12000 16000 1 2 3 4 5 6 7 8 9 10 Area (um^2) 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 Energy (pJ/pkt)

Number of router ports

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

Generated RTL

Number of router ports

Area/Energy analysis of router

Injection rate Injection rate Injection rate

Simulation of different topologies at different injection rates

Area Budget Energy Budget

slide-16
SLIDE 16

Cheng Tan Cornell University 16/20

PyOCN for Evaluating OCNs

  • Placement of butterfly topology

– 64-terminal 4-ary 3-fly butterfly topology – 3 routers in the same row can be recognized as a router group Case study to show the features of PyOCN

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7 RG8 RG9 RG10 RG11 RG12 RG13 RG14 RG15

Critical paths

slide-17
SLIDE 17

net = BFlyNetworkRTL( pkt_t, k_ary=4, n_fly=3 ) critical_paths = [ “channels[82]”, “channels[114]”, … ] for c in critical_paths: net.set_param( f’top.{c}.construct’, hops=2 ) net.elaborate()

RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7 RG8 RG9 RG10 RG11 RG12 RG13 RG14 RG15

Cheng Tan Cornell University 17/20

PyOCN for Evaluating OCNs

  • Placement of butterfly topology

– 64-terminal 4-ary 3-fly butterfly topology – 3 routers in the same row can be recognized as a router group

  • Parameterization system

– use set_param() to break down.

Critical paths

Case study to show the features of PyOCN

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

slide-18
SLIDE 18

Cheng Tan Cornell University 18/20

PyOCN for Evaluating OCNs

  • Placement of butterfly topology

– 64-terminal 4-ary 3-fly butterfly topology – 3 routers in the same row can be recognized as a router group

  • Parameterization system

– use set_param() to break down. Case study to show the features of PyOCN

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

slide-19
SLIDE 19

Cheng Tan Cornell University 19/20

Open-Source PyOCN

  • Open-source

– https://github.com/cornell-brg/pymtl3-net

  • Demo

To create a virtual environment and install pymtl3-net: % python3 -m venv ${HOME}/venv % source ${HOME}/venv/bin/activate % pip3 install pymtl3-net To test a 4-terminal ring using single-pkt with dumped vcd: % pymtl3-net test ring --nterminals 4 --dump-vcd To simulate a 2x2 mesh with specific injection rate: % pymtl3-net sim mesh --ncols 2 --nrows 2 --injection-rate 10 -v To simulate a 2x2 mesh across different injection rates: % pymtl3-net sim mesh --ncols 2 --nrows 2 --sweep -v To generate a 4x4 mesh: % pymtl3-net gen mesh --ncols 4 --nrows 4 PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

Repl.it: https://repl.it/@ChengTan/pyocn-demo

slide-20
SLIDE 20

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

Cheng Tan Cornell University 20/20

OCN Config. FL model CL model RTL model PL model SoC Simulator Network Lib. Channel Lib. Router Lib. InputUnit Lib. RouteUnit Lib. SwitchUnit Lib. OutputUnit Lib. PyOCN

  • Std. Lib

EDA toolflow CL Perf. stats RTL Perf. stats AET stats Floor- plan Verilog

Characterizing Generating

Testing Modeling Evaluating

Simulating

Param. System PyMTL Elaborate Test Harness PyMTL

  • Sim. Pass

PyMTL

  • Sim. Pass

PyMTL

  • Sim. Pass

PBRT Tester Integration Tester Unit Tester PyMTL

  • Gen. Pass

PyOCN EDA script PyMTL

  • Place. Pass

PyOCN Simulator

  • Enables multi-level modeling to facilitate rapid design-space exploration
  • Provides test harnesses for testing OCN designs modeled at different abstraction levels
  • Can simulate OCNs at various abstraction levels, generate synthesizable Verilog, and drive a

commercial standard-cell-based toolflow for characterizing OCN area, energy, and timing

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

This work was supported in part by NSF CRI Award #1512937, DARPA POSH Award #FA8650-18-2-7852, and equipment, tool, and/or physical IP donations from Intel, Synopsys, and Cadence.