MIXED-TIME SIGNAL TEMPORAL LOGIC FORMATS 2019 Thomas Ferrre IST - - PowerPoint PPT Presentation

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MIXED-TIME SIGNAL TEMPORAL LOGIC FORMATS 2019 Thomas Ferrre IST Austria Oded Maler VERIMAG Dejan Nickovic AIT Austrian Institute of Technology INTRODUCTION Cyber-Physical Systems (CPS) Heterogeneous components Informal

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SLIDE 1

MIXED-TIME SIGNAL TEMPORAL LOGIC

FORMATS 2019

Thomas Ferrère – IST Austria Oded Maler – VERIMAG Dejan Nickovic – AIT Austrian Institute of Technology

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SLIDE 2
  • Cyber-Physical Systems (CPS)
  • Heterogeneous components
  • SW, Sensors, Actuations, uC, etc.
  • CPS are often safety critical
  • → model-based development (MBD)
  • → verification and testing
  • Specification-based testing for CPS
  • Signal Temporal Logic (STL)
  • Declarative properties of CPS
  • STL monitoring as basic technology

INTRODUCTION

2 Informal Requirement STL Specification

SUT p1 Parameters p2 Input Stimuli Monitor Verdict

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SLIDE 3

3 05/09/2019

HETEROGENEITY OF CPS

  • Specification-based testing for CPS
  • STL: only dense interpretation of time
  • Sensors, actuators, analog components
  • Dense time
  • Digital controllers
  • Discrete (clocked) time
  • How to specify and evaluate system-

level properties with different time domains?

  • Heterogeneous components in CPS
  • MBD with heterogeneous models of

computation

  • Ptolemy
  • MathWorks tools
  • Simulink, SimScape, SimEvents, etc.
  • Scade
  • Verilog AMS, VHDL AMS
  • What about verification and testing?
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SLIDE 4
  • Bounded stabilization property
  • Digital command 𝑑𝑛𝑒
  • Analog response 𝑦
  • Whenever 𝑑𝑛𝑒 is on its rising edge, the

absolute value of 𝑦 must become lower than 1 within 600 time units and remain continuously within that range for at least 300 time units

  • Sampling period 𝑈 = 200 time units

4 05/09/2019

MOTIVATING EXAMPLE

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SLIDE 5
  • Two specification layers
  • Discrete-time layer 𝜒
  • LTL with past
  • Continuous-time layer 𝛽
  • STL with past
  • Time mapping operators to “switch”

between layers

  • @𝒆𝒅 - from discrete to continuous-time

layer

  • @𝒅𝒆 - from continuous to discrete-time

layer

5 05/09/2019

MIXED-TIME SIGNAL TEMPORAL LOGIC (STL-MX)

  • Syntax

𝜒 ≔ 𝑞 ¬𝜒 𝜒1 ∨ 𝜒2 𝑌 𝜒 𝑄 𝜒 𝜒1𝑉𝜒2 𝜒1𝑇𝜒2 | @𝑑𝑒(𝛽) 𝛽 ≔ 𝑦 ≼ 𝑑 ¬𝑏 𝛽1 ∨ 𝛽2 𝛽1𝑉𝐽𝛽2 𝛽1𝑇𝐽𝛽2 | @𝑒𝑑(𝜒)

  • 𝑌 – next, 𝑄 – previously, 𝑉 – until, 𝑇 – since
  • Other combinatorial and temporal operators derived in

standard way

  • ∧, →, ↔
  • 𝐻 – always, 𝐺 – eventually
  • 𝐼 – historically, 𝑃 - once
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SLIDE 6

Time mapping operators

  • 𝑞 = @𝑑𝑒(𝑧)

6 05/09/2019

STL-MX SEMANTICS

  • 𝑧 = @𝑒𝑑(𝑞)

𝑞 𝑧 𝑞 𝑧

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SLIDE 7
  • Whenever 𝑑𝑛𝑒 is on its rising edge, the

absolute value of 𝑦 must become lower than 1 within 600 time units and remain continuously within that range for at least 300 time units

  • Sampling period 𝑈 = 200 time units
  • STL-MX specification

𝐻( 𝑄¬𝑑𝑛𝑒 ∧ 𝑑𝑛𝑒 → @𝑑𝑒 𝐺 0,600 𝐻 0,300 𝑦 ≤ 1 )

7 05/09/2019

MOTIVATING EXAMPLE REVISITED

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SLIDE 8
  • Discrete-time formula equivalence
  • 𝜒 ∼ 𝜒′ iff for all signals 𝑣, 𝑥 and time indices 𝑗, 𝑣, 𝑥, 𝑗 ⊨𝑒 𝜒 ↔ 𝑣, 𝑥, 𝑗 ⊨𝑒 𝜒′
  • Continuous-time formula equivalence
  • 𝛽 ∼ 𝛽′ iff for all signals 𝑣, 𝑥 and real time values 𝑢, 𝑣, 𝑥, 𝑢 ⊨𝑑 𝛽 ↔ 𝑣, 𝑥, 𝑢 ⊨𝑑 𝛽′

STL-MX FORMULA EQUIVALENCE

8 05/09/2019

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SLIDE 9
  • For all 𝜒, 𝜒 = @𝑑𝑒@𝑒𝑑(𝜒)

9 05/09/2019

STL-MX PROPERTIES

  • There exists 𝛽, s.t. 𝛽 ≠ @𝑒𝑑@𝑑𝑒(𝛽)

@𝑑𝑒(𝑧) 𝑧 @𝑒𝑑@𝑑𝑒(𝑧) 𝑞 @𝑑𝑒@𝑒𝑑(𝑞) @𝑑𝑒 (𝑞)

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SLIDE 10
  • Time mapping operators commute over Boolean connectives

STL-MX PROPERTIES

10 05/09/2019

@𝑒𝑑 ¬𝜒 = ¬@𝑒𝑑(𝜒) @𝑒𝑑 𝜒1 ∨ 𝜒2 = @𝑒𝑑 𝜒1 ∨ @𝑒𝑑(𝜒2) @𝑑𝑒 ¬𝛽 = ¬@𝑑𝑒(𝛽) @𝑑𝑒 𝛽1 ∨ 𝛽2 = @𝑑𝑒 𝛽1 ∨ @𝑑𝑒(𝛽2)

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SLIDE 11
  • STL-MX ≈ STL + clock event 𝑑𝑚𝑙
  • Example: clock event 𝑑𝑚𝑙 with period 𝑈 is

continuous time signal

  • 𝑢𝑠𝑣𝑓 at multiples of 𝑈
  • 𝑔𝑏𝑚𝑡𝑓 otherwise
  • Every STL-MX formula can be

mapped to STL

  • Syntactic mapping 𝜏
  • → Polynomial-time reduction

11 05/09/2019

EXPRESSIVITY OF STL-MX

STL-MX to STL mapping

  • 𝜏 𝑞 = 𝑞
  • 𝜏 𝑌𝜒 = ¬𝑑𝑚𝑙𝑉(0,∞) 𝑑𝑚𝑙 ∧ 𝜏 𝜒
  • 𝜏 𝜒1𝑉𝜒2 = 𝜏 𝜒2 ∨ (𝜏 𝜒1 𝑉 0,∞ 𝜏 𝜒2 )
  • 𝜏 @𝑑𝑒 𝛽

= ¬𝑑𝑚𝑙 𝑇(𝑑𝑚𝑙 ∧ 𝜏 𝛽 )

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SLIDE 12
  • Discrete-time part
  • → LTL monitor – temporal testers
  • Dense-time part
  • → STL monitor – temporal testers
  • Combining LTL + STL monitors
  • → time mapping operators
  • Monitor for @𝒅𝒆
  • Monitor for @𝒆𝒅

12 05/09/2019

MONITORING STL-MX

LTL Monitor Time mapping operator STL Monitor ¬ 𝑄 ∧ → | ⋅ | < 1 𝐻[0,300] 𝐺

[0,600]

@𝑑𝑒 Monitor for the bounded stabilization property

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SLIDE 13

Monitor for @𝒅𝒆

  • Input: CT signal 𝑣, sampling period 𝑈
  • Output: DT signal 𝑥 = @𝑑𝑒(𝑣)
  • 𝐽 𝑣 = 𝐽1 ⋅ 𝐽2 ⋯ 𝐽𝑜 is a time partition consistent

with 𝑣

  • 𝑙 ∶= 0
  • for every time interval 𝐽

𝑘

  • while 𝑙𝑈 ∈ 𝐽

𝑘

  • 𝑥 𝑙 = 𝑣(𝐽

𝑘)

  • 𝑙 ∶= 𝑙 + 1

13 05/09/2019

MONITORING STL-MX

Monitor for @𝒆𝒅

  • Input: DT signal 𝑥, sampling period 𝑈
  • Output: CT signal 𝑣 = @𝑒𝑑(𝑥)
  • for every time index 𝑙 in 𝑥
  • 𝐽𝑙 = [𝑙𝑈, 𝑙 + 1 𝑈)
  • 𝑣 𝐽𝑙 = 𝑥(𝑙)
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SLIDE 14
  • Δ − Σ modulator
  • Subtractor
  • 𝑣Δ(𝑢) = 𝑣𝑗𝑜 𝑢 − 𝑣𝑞𝑚𝑡(𝑢)
  • Integrator
  • 𝑣Σ 𝑢 = 𝐵 ⋅ ׬

𝑢 𝑣Δ 𝑢′ 𝑒𝑢′

  • Threshold
  • 𝑞𝑝𝑣𝑢 𝑗 = ቊ1, 𝑣Σ 𝑗𝑈 ≥ 𝑤0

0, 𝑝𝑢ℎ𝑓𝑠𝑥𝑗𝑡𝑓

  • Pulse
  • 𝑣𝑞𝑚𝑡 𝑢 = ቐ𝑤1, 𝑞𝑝𝑣𝑢

𝑢 𝑈 − 1 = 0 ∧ 𝑞𝑝𝑣𝑢 𝑢 𝑈

= 1 𝑤0, 𝑝𝑢ℎ𝑓𝑠𝑥𝑗𝑡𝑓

  • Sampling period 𝑈 = 3.2𝜈𝑡

14 05/09/2019

CASE STUDY: Δ − Σ MODULATOR

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SLIDE 15

Property 1

  • When we observe a rising edge in the
  • utput, the voltage out of the integrator

has to return to a value below the threshold at the next clock tick

  • STL-MX specification 𝜒1:

𝐻( 𝑄¬𝑞𝑝𝑣𝑢 ∧ 𝑞𝑝𝑣𝑢 → 𝑌@𝑑𝑒(𝑣Σ < 𝑤0)

15 05/09/2019

CASE STUDY: PROPERTY SPECIFICATION

Property 2

  • When the input voltage is above 1.05𝑊

for 12.8𝜈𝑡 the output must have a sequence of two consecutive spikes starting over that time frame

  • STL-MX specification 𝜒2:

𝐻(𝐻 0,12.8 𝑣𝑗𝑜 > 1.05 → 𝐺 0,12.8 @𝑒𝑑 ¬𝑞𝑝𝑣𝑢 ∧ 𝑌𝑞𝑝𝑣𝑢 ∧ 𝑌2¬𝑞𝑝𝑣𝑢 ∧ 𝑌3𝑞𝑝𝑣𝑢 )

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SLIDE 16

CASE STUDY: SIMULATION AND EVALUATION

16 05/09/2019

𝒗𝒋𝒐 𝒖 = 𝟏. 𝟕 𝒅𝒑𝒕 𝟐𝟏𝟏𝟏 ⋅ 𝟑𝝆 ⋅ 𝒖 + 𝟏. 𝟕 𝒗𝒋𝒐 𝒖 = 𝟏. 𝟖 𝒅𝒑𝒕 𝟐𝟏𝟏𝟏 ⋅ 𝟑𝝆 ⋅ 𝒖 + 𝟏. 𝟖

𝝌𝟐 satisfied 𝝌𝟐 violated

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SLIDE 17

CASE STUDY: EXECUTION TIMES

17 05/09/2019

Property Sim # 𝒗𝚻 𝒗𝒋𝒐 𝒒𝒑𝒗𝒖 time(𝒏𝒕) 𝜒1 1 20,470 727 143 𝜒1 2 2,771 58 104 𝜒2 3 26,207 971 45 𝜒2 4 27,926 971 50 𝜒2 5 29,495 971 51 𝜒2 6 31,298 1,212 58 𝜒2 7 32,133 1,212 59 𝜒2 8 33,005 1,212 61

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SLIDE 18
  • STL-MX specification 𝜒2:

𝐻(𝐻 0,12.8 𝑣𝑗𝑜 > 1.05 → 𝐺 0,12.8 @𝑒𝑑 ¬𝑞𝑝𝑣𝑢 ∧ 𝑌𝑞𝑝𝑣𝑢 ∧ 𝑌2¬𝑞𝑝𝑣𝑢 ∧ 𝑌3𝑞𝑝𝑣𝑢 )

  • STL specification 𝜏 𝜒2 :

𝐻(𝐻 0,12.8 𝑣𝑗𝑜 > 1.05 → 𝐺 0,12.8 ¬𝑞𝑝𝑣𝑢 ∧ ¬𝑑𝑚𝑙𝑉(𝑑𝑚𝑙 ∧ 𝑞𝑝𝑣𝑢) ∧ ¬𝑑𝑚𝑙𝑉𝑑𝑚𝑙 ∧ (¬𝑑𝑚𝑙𝑉 𝑑𝑚𝑙 ∧ ¬𝑞𝑝𝑣𝑢 ) ∧ ¬𝑑𝑚𝑙𝑉𝑑𝑚𝑙 ∧ (¬𝑑𝑚𝑙𝑉 𝑑𝑚𝑙 ∧ ¬𝑑𝑚𝑙𝑉 𝑑𝑚𝑙 ∧ 𝑞𝑝𝑣𝑢 ) )

CASE STUDY: STL-MX VS. STL

18 05/09/2019

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SLIDE 19
  • Automatic insertion of @cd and @dc conversion operators based on type inference
  • Facilitate use of the specification language
  • More sophisticated conversion operators
  • Instead of periodic sample and hold.
  • Truth value of discrete signal depends on integrating values at continuous time in some interval

around it

  • Event-based conversion in asynchronous style
  • Tighter interaction between the monitoring procedure and the simulators
  • Equipping STL-mx with quantitative semantics

FUTURE WORK

19 05/09/2019

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SLIDE 20
  • STL-MX
  • Syntactic and semantic constructs
  • Co-existence of discrete and continuous-time specifications
  • Main application - runtime monitoring of CPS and mixed signal designs
  • Step towards system-wide specification-based verification

CONCLUSIONS

20 05/09/2019

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SLIDE 21

THANK YOU!

Lecturer, Date