Microsoft’s Production Configurable Cloud
Derek Chiou Microsoft Azure Cloud Silicon UT Austin
H2RC Nov 14, 2016 1
Microsofts Production Configurable Cloud Derek Chiou Microsoft - - PowerPoint PPT Presentation
Microsofts Production Configurable Cloud Derek Chiou Microsoft Azure Cloud Silicon UT Austin H2RC Nov 14, 2016 1 Todays Data Centers O(100K) servers/data center Very dense, maximize number of servers Tens of MegaWatts
Derek Chiou Microsoft Azure Cloud Silicon UT Austin
H2RC Nov 14, 2016 1
place, etc.
improvement to make sense
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ASICs
Source: Bob Broderson, Berkeley Wireless group
FPGAs
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Depends on your point of view
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DRAM CPU network Storage
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Acc DRAM CPU network Storage
Network “offload”
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NIC DRAM Acc Acc Acc CPU network Storage
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network DRAM CPU FPGA Storage DRAM CPU DRAM Acc
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with
app state consistent
FPGA!
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CPU CPU FPGA NIC DRAM DRAM DRAM
WCS 2.0 Server Blade Catapult V2
Gen3 2x8 Gen3 x8 QPI Switch QSFP QSFP QSFP 40Gb/s 40Gb/s
WCS Gen4.1 Blade with Mellanox NIC and Catapult FPGA
Pikes Peak WCS Tray Backplane
Option Card Mezzanine Connectors
Catapult v2 Mezzanine card
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IFM 1 IFM 2 IFM 44 IFM 3 IFM 1 IFM 2 IFM 44 IFM 3 IFM 1 IFM 2 IFM 44 IFM 3
SaaS 1 SaaS 2 SaaS 48 SaaS 3
Ranki king-as as-a-Service (RaaS) )
document is for the search query
Sele lectio ion-as as-a-Service (S (SaaS)
ranking Sele lectio ion as s a Serv rvice ice (S (SaaS)
IFM 1 IFM 2 IFM 44 IFM 3 IFM 1 IFM 2 IFM 44 IFM 3 IFM 1 IFM 2 IFM 44 IFM 3 RaaS 1 RaaS 2 RaaS 48 RaaS 3
Ranki king as s a Serv rvic ice (RaaS)
Qu Query Sel Selecte ted Do Documents ts
10 10 blu lue lin links ks
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Query: “FPGA Configuration”
NumberOfOccurrences_0 = 7 NumberOfOccurrences_1 = 4 NumberOfTuples_0_1 = 1
{Query, Document} ~4K Dynamic Features ~2K Synthetic Features L2 Score
Docu cument Sco core re
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PCIe Distribution latches Control/Data Tokens Compressed Document
Feature Gathering Network Free Form Expression (FFE) Stream Preprocessing FSM
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software FPGA 99.9% Query Latency versus Queries/sec
HW vs. SW Latency and Load average software load 99.9% software latency 99.9% FPGA latency average FPGA query load
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much faster than single server
FPGA resources
and save FPGA resources
single FPGA?
requests and return responses
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ToR
FPGA NIC Server FPGA NIC Server FPGA NIC Server FPGA NIC Server
CS0 CS1 CS2 CS3 ToR
FPGA NIC Server FPGA NIC Server FPGA NIC Server FPGA NIC Server
SP0 SP1 SP2 SP3
their own UDP packets
communication (LTL)
network primitives
up other opportunities
L0 L1/L2
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5 10 15 20 25 1 10 100 1000 10000 100000 1000000
Round-Trip Latency (us) LTL L0 (same TOR) LTL L1
Example L0 latency histogram Example L1 latency histogram Examples of L2 latency histograms for different pairs of FPGAs
Number of Reachable Hosts/FPGAs 6x8 Torus
(can reach up to 48 FPGAs)
LTL Average Latency LTL 99.9th Percentile 6x8 Torus Latency
LTL L2
10K 100K 250K
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ToR ToR CS CS ToR ToR Bing Ranking SW
HPC
Bing Ranking HW
Speech to text Large-scale deep learning
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many FPGAs as needed (up to thousands)
FPGA execution
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than CPU implementation
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SLB Decap SLB NAT VNET ACL Metering
Rule Action Rule Action Rule Action Rule Action Rule Action Rule Action Decap * DNAT * Rewrite * Allow * Meter *SmartNIC
VFP
VMSwitch VM
SR-IOV (Host Bypass)
50G
QoS
Crypto RDMA
Flow Action
Decap, DNAT, Rewrite, Meter 1.2.3.1->1.3.4.1, 62362->80GFT
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sends messages with no OS/hypervisor call
packet, rewrites header to make data center compatible
metal
cloud network
NIC VFP Hypervisor Guest OS VM NIC VM GFT/FPGA
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fabric?
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