Memory System Design: Virtual Memory Virendra Singh Associate - - PowerPoint PPT Presentation

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Memory System Design: Virtual Memory Virendra Singh Associate - - PowerPoint PPT Presentation

May 07, 2023 139 likes •428 views

Memory System Design: Virtual Memory Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:

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Memory System Design:

Virtual Memory

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-739: Processor Design

Lecture 20 (04 Mar 2013)

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Performance: Miss

  • Miss rate
  • Fraction of cache access that result in a miss
  • Causes of misses
  • Compulsory
  • First reference to a block
  • Capacity
  • Blocks discarded and later retrieved
  • Conflict
  • Program makes repeated references to multiple

addresses from different blocks that map to the same location in the cache

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  • Reducing miss rate
  • Larger block size, larger cache size, higher

associativity

  • Reducing miss penalty
  • Multi-level caches, read priority over write
  • Reducing time to hit in the cache
  • Avoid address translation when indexing caches

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Memory Optimization

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Memory Hierarchy Basics

  • Six basic cache optimizations:
  • Larger block size
  • Reduces compulsory misses
  • Increases capacity and conflict misses, increases

miss penalty

  • Larger total cache capacity to reduce miss

rate

  • Increases hit time, increases power consumption
  • Higher associativity
  • Reduces conflict misses
  • Increases hit time, increases power consumption

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Memory Hierarchy Basics

  • Six basic cache optimizations:
  • Higher number of cache levels
  • Reduces overall memory access time
  • Giving priority to read misses over writes
  • Reduces miss penalty
  • Avoiding address translation in cache

indexing

  • Reduces hit time

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Summary Summary

  • Memory technology
  • Memory hierarchy

– Temporal and spatial locality

  • Caches

– Placement – Identification – Replacement – Write Policy

  • Pipeline integration of caches

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Memory Hierarchy Memory Hierarchy

CPU I & D L1 Cache Shared L2 Cache Main Memory Disk Temporal Locality

  • Keep recently

referenced items at higher levels

  • Future references

satisfied quickly Spatial Locality

  • Bring neighbors of

recently referenced to higher levels

  • Future references

satisfied quickly

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Four Burning Issues Four Burning Issues

  • These are:

– Placement

  • Where can a block of memory go?

– Identification

  • How do I find a block of memory?

– Replacement

  • How do I make space for new blocks?

– Write Policy

  • How do I propagate changes?
  • Consider these for registers and main memory

– Main memory usually DRAM

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Placement Placement

Memory Type Placement Comments Registers Anywhere; Int, FP, SPR Compiler/programme r manages Cache (SRAM) Fixed in H/W Direct-mapped, set-associative, fully-associative DRAM Anywhere O/S manages Disk Anywhere O/S manages

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Register File Register File

  • Registers managed by programmer/compiler

– Assign variables, temporaries to registers – Limited name space matches available storage

Placement Flexible (subject to data type) Identification Implicit (name == location) Replacement Spill code (store to stack frame) Write policy Write-back (store on replacement)

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Main Memory and Virtual Memory Main Memory and Virtual Memory

  • Use of virtual memory

– Main memory becomes another level in the memory hierarchy – Enables programs with address space or working set that exceed physically available memory

  • No need for programmer to manage overlays, etc.
  • Sparse use of large address space is OK

– Allows multiple users or programs to timeshare limited amount of physical memory space and address space

  • Bottom line: efficient use of expensive resource,

and ease of programming

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Virtual Memory Virtual Memory

  • Enables

– Use more memory than system has – Program can think it is the only one running

  • Don’t have to manage address space usage across

programs

  • E.g. think it always starts at address 0x0

– Memory protection

  • Each program has private VA space: no-one else

can clobber

– Better performance

  • Start running a large program before all of it has

been loaded from disk

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Virtual Memory – Placement Virtual Memory – Placement

  • Main memory managed in larger blocks

– Page size typically 4K – 16K

  • Fully flexible placement; fully associative
  • Operating system manages placement
  • Indirection through page table
  • Maintain mapping between:
  • Virtual address (seen by programmer)
  • Physical address (seen by main memory)

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Virtual Memory – Placement Virtual Memory – Placement

  • Fully associative implies expensive

lookup?

– In caches, yes: check multiple tags in parallel

  • In virtual memory, expensive lookup is

avoided by using a level of indirection

– Lookup table or hash table – Called a page table

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Virtual Memory – Identification Virtual Memory – Identification

  • Similar to cache tag array

– Page table entry contains VA, PA, dirty bit

  • Virtual address:

– Matches programmer view; based on register values – Can be the same for multiple programs sharing same system, without conflicts

  • Physical address:

– Invisible to programmer, managed by O/S – Created/deleted on demand basis, can change

Virtual Address Physical Address Dirty bit 0x20004000 0x2000 Y/N

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Virtual Memory – Replacement Virtual Memory – Replacement

  • Similar to caches:

– FIFO – LRU; overhead too high

  • Approximated with reference bit checks
  • Clock algorithm

– Random

  • O/S decides, manages

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Virtual Memory – Write Policy Virtual Memory – Write Policy

  • Write back

– Disks are too slow to write through

  • Page table maintains dirty bit

– Hardware must set dirty bit on first write – O/S checks dirty bit on eviction – Dirty pages written to backing store

  • Disk write, 10+ ms

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Virtual Memory Implementation Virtual Memory Implementation

  • Caches have fixed policies, hardware

FSM for control, pipeline stall

  • VM has very different miss penalties

– Remember disks are 10+ ms!

  • Hence engineered differently

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Page Faults Page Faults

  • A virtual memory miss is a page fault

– Physical memory location does not exist – Exception is raised, save PC – Invoke OS page fault handler

  • Find a physical page (possibly evict)
  • Initiate fetch from disk

– Switch to other task that is ready to run – Interrupt when disk access complete – Restart original instruction

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Address Translation Address Translation

  • O/S and hardware communicate via

PTE

  • How do we find a PTE?

– &PTE = PTBR + page number * sizeof(PTE) – PTBR is private for each program

  • Context switch replaces PTBR contents

VA PA Dirty Ref Protection 0x2000400 0x2000 Y/N Y/N Read/Write /Execute

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Address Translation Address Translation

PA VA D PTBR Virtual Page Number Offset +

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Page Table Size Page Table Size

  • How big is page table?

– 232 / 4K * 4B = 4M per program (!) – Much worse for 64-bit machines

  • To make it smaller

– Use limit register(s)

  • If VA exceeds limit, invoke O/S to grow region

– Use a multi-level page table – Make the page table pageable (use VM)

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Multilevel Page Table Multilevel Page Table

PTBR + Offset + +

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Hashed Page Table Hashed Page Table

  • Use a hash table or inverted page table

– PT contains an entry for each real address

  • Instead of entry for every virtual address

– Entry is found by hashing VA – Oversize PT to reduce collisions: #PTE = 4 x (#phys. pages)

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Hashed Page Table Hashed Page Table

PTBR Virtual Page Number Offset Hash

PTE2 PTE1 PTE0 PTE3 04 Mar 2013

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High-Performance VM High-Performance VM

  • VA translation

– Additional memory reference to PTE – Each instruction fetch/load/store now 2 memory references

  • Or more, with multilevel table or hash collisions

– Even if PTE are cached, still slow

  • Hence, use special-purpose cache for PTEs

– Called TLB (translation lookaside buffer) – Caches PTE entries – Exploits temporal and spatial locality (just a cache)

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TLB TLB

04 Mar 2013