Memory Management Disclaimer: some slides are adopted from book - - PowerPoint PPT Presentation

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Memory Management Disclaimer: some slides are adopted from book - - PowerPoint PPT Presentation

Oct 18, 2022 192 likes •484 views

Memory Management Disclaimer: some slides are adopted from book authors slides with permission 1 Recap: Virtual Memory (VM) Process A Process C Process B MMU 2 Physical Memory Recap: MMU Hardware that translates virtual addresses to

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SLIDE 1

Memory Management

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Disclaimer: some slides are adopted from book authors’ slides with permission

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SLIDE 2

Recap: Virtual Memory (VM)

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Process A Process B Process C Physical Memory

MMU

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SLIDE 3

Recap: MMU

  • Hardware that translates virtual addresses to

physical addresses

1) base register 2) base + limit registers (segmentation); 3) paging

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SLIDE 4

Recap: Page Table based Address Translation

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0x12345678

Ox12345 0x678

Page # Offset frame #: 0xabcde frame #

  • ffset

0x678 0x12345

0xabcde678

Virtual address Physical address Page table

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SLIDE 5

Advantages of Paging

  • No external fragmentation

– Efficient use of memory – Internal fragmentation (waste within a page) still exists

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SLIDE 6

Issues of Paging

  • Translation speed

– Each load/store instruction requires a translation – Table is stored in memory – Memory is slow to access

  • ~100 CPU cycles to access DRAM

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SLIDE 7

Translation Lookaside Buffer (TLB)

  • Cache frequent address translations

– So that CPU don’t need to access the page table all the time – Much faster

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SLIDE 8

Issues of Paging

  • Page size

– Small: minimize space waste, requires a large table – Big: can waste lots of space, the table size is small – Typical size: 4KB – How many pages are needed for 4GB (32bit)?

  • 4GB/4KB = 1M pages

– What is the required page table size?

  • assume 1 page table entry (PTE) is 4bytes
  • 1M * 4bytes = 4MB

– Btw, this is for each process. What if you have 100 processes? Or what if you have a 64bit address?

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SLIDE 9

Paging

  • Advantages

– No external fragmentation

  • Two main Issues

– Translation speed can be slow

  • TLB

– Table size is big

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SLIDE 10

Multi-level Paging

  • Two-level paging

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SLIDE 11

Two Level Address Translation

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2nd level

  • ffset

1st level 1st level Page table 2nd level Page table

Frame # Offset Base ptr

Virtual address Physical address

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SLIDE 12

Example

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2nd level

  • ffset

8 bits 8 bits

1st level

8 bits Virtual address format (24bits) Vaddr: 0x0703FE 1st level idx: 07 2nd level idx: 03 Offset: FE Vaddr: 0x072370 1st level idx: __ 2nd level idx: __ Offset: __ Vaddr: 0x082370 1st level idx: __ 2nd level idx: __ Offset: __

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SLIDE 13

Multi-level Paging

  • Can save table space
  • How, why?

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SLIDE 14

Summary

  • MMU

– Virtual address  physical address – Various designs are possible, but

  • Paged MMU

– Memory is divided into fixed-sized pages – Use page table to store the translation table – No external fragmentation: i.e., efficient space utilization

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SLIDE 15

Virtual Memory (VM)

  • Abstraction

– 4GB linear address space for each process

  • Reality

– 1GB of actual physical memory shared with 20

  • ther processes
  • Does each process use the

(1) entire virtual memory (2) all the time?

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SLIDE 16

Concepts to Learn

  • Demand paging

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SLIDE 17

Demand Paging

  • Idea: instead of keeping the entire memory

pages in memory all the time, keep only part

  • f them on a on-demand basis

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SLIDE 18

Page Table Entry (PTE)

  • PTE format (architecture specific)

– Valid bit (V): whether the page is in memory – Modify bit (M): whether the page is modified – Reference bit (R): whether the page is accessed – Protection bits(P): readable, writable, executable

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Page Frame No V M R P 20 bits 2 1 1 1

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SLIDE 19

Partial Memory Mapping

  • Not all pages are in memory (i.e., valid=1)

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SLIDE 20

Page Fault

  • When a virtual address can not be translated

to a physical address, MMU generates a trap to the OS

  • Page fault handling procedure

– Step 1: allocate a free page frame – Step 2: bring the stored page on disk (if necessary) – Step 3: update the PTE (mapping and valid bit) – Step 4: restart the instruction

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SLIDE 21

Page Fault Handling

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SLIDE 22

Demand Paging

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SLIDE 23

Starting Up a Process

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Unmapped pages

Code Data Heap Stack

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SLIDE 24

Starting Up a Process

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Access next instruction

Code Data Heap Stack

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SLIDE 25

Starting Up a Process

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Page fault

Code Data Heap Stack

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SLIDE 26

Starting Up a Process

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OS 1) allocates free page frame 2) loads the missed page from the disk (exec file) 3) updates the page table entry

Code Data Heap Stack

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SLIDE 27

Starting Up a Process

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Code Data Heap Stack

Over time, more pages are mapped as needed

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SLIDE 28

Anonymous Page

  • An executable file contains code (binary)

– So we can read from the executable file

  • What about heap?

– No backing storage (unless it is swapped out later) – Simply map a new free page (anonymous page) into the address space

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SLIDE 29

Program Binary Sharing

  • Multiple instances of the same program

– E.g., 10 bash shells

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Bash text Physical memory Bash #1 Bash #2