MemoryManagementUnit VirtualMemory ThepositionandfunctionoftheMMU - - PDF document

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VirtualMemory

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MemoryManagementUnit

ThepositionandfunctionoftheMMU

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• VirtualMemory

– Dividedintoequal sized – A isa translationbetween

• Apageandaframe
• Apageandnull

– Mappingsdefinedat runtime

• Theycanchange

– Addressspacecan haveholes – Processdoesnot havetobe contiguousin physicalmemory

• PhysicalMemory

– Dividedinto equal sized

• 7

6 5 4 3 2 1 15 14 13 12 11 10 9 8 1 12 10 2 3 11 VirtualAddress Space PhysicalAddress Space

Paging

1 2 3 4 5 6 7

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TypicalAddress SpaceLayout

• Stackregionisattop,

andcangrowdown

• Heaphasfreespaceto

growup

• Textistypicallyread only
• Kernelisinareserved,

protected,sharedregion

• 0 thpagetypicallynot

used,why? 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 VirtualAddress Space Kernel Stack Shared Libraries BSS (heap) Data Text (Code)

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• Aprocessmay

beonlypartially resident

– AllowsOSto storeindividual pagesondisk – Savesmemory forinfrequently useddata&code

• Whathappensif

weaccessnon resident memory?

1 15 5 3 13 VirtualAddress Space PhysicalAddress Space 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 14 10 6 4 2 Disk : logicallypresent :Not mapped,dataondisk

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2 4 13 4 1 3 13 Proc1Address Space

Physical AddressSpace

7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 Proc2Address Space 3 15 15 1 2 14 14 Disk

Currently running

Memory Access 2

2

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PageFaults

• Referencinganinvalidpagetriggersapagefault
• AnexceptionhandledbytheOS
• Broadly,twostandardpagefaulttypes

– IllegalAddress(protectionerror)

• Signalorkilltheprocess

– Pagenotresident

• Getanemptyframe
• Loadpagefromdisk
• Updatepage(translation)table(enterframe#,setvalidbit,etc.)
• Restartthefaultinginstruction

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• Pagetablefor

residentpartof addressspace

1 15 5 4 5 2 3 13 VirtualAddress Space Physical AddressSpace 7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 3 1 7 6 Page Table 1 2 3 4 5 6 7

• Note:Someimplementationsstoredisk

blocknumbersofnon residentpagesin thepagetable(withvalidbit)

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SharedPages

• Privatecodeanddata

– Eachprocesshasown copyofcodeanddata – Codeanddatacan appearanywherein theaddressspace

• Sharedcode

– Singlecopyofcode sharedbetweenall processesexecutingit – Codemustnotbeself modifying – Codemustappearat sameaddressinall processes

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2 6 13 4 3 1 3 13 Proc1Address Space

Physical AddressSpace

7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 2 5 4 7 Page Table 7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 1 2 7 Proc2Address Space Page Table

Two(ormore) processes runningthe sameprogram andsharing thetextsection

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PageTableStructure

• Pagetableis(logically)anarrayof

framenumbers

– Indexbypagenumber

• Eachpage tableentry(PTE)alsohas
• therbits

2 5 4 7 Page Table

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PTEbits

• Present/Absentbit

– Alsocalleditindicatesavalidmappingforthepage

• Modifiedbit

– Alsocalleditindicatesthepagemayhavebeen modifiedinmemory

• Referencebit

– Indicatesthepagehasbeenaccessed

• Protectionbits

– Readpermission,Writepermission,Executepermission – Orcombinationsoftheabove

• Cachingbit

– Usetoindicateprocessorshouldbypassthecachewhen accessingmemory

• Example:toaccessdeviceregistersormemory

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AddressTranslation

• Every(virtual)memoryaddressissuedby

theCPUmustbetranslatedtophysical memory

– Every andevery instruction – Everyinstructionfetch

• NeedTranslationHardware
• Inpagingsystem,translationinvolves

replacepagenumberwithaframenumber

Pagetables(recap) virtualmemory

virtualandphysicalmemchoppedupinpages

• !
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PageTables

• Assumewehave

– 32 bitvirtualaddress(4Gbyteaddressspace) – 4KBytepagesize – Howmanypagetableentriesdoweneedforone process?

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PageTables

• Assumewehave

– 64 bitvirtualaddress(humungous addressspace) – 4KBytepagesize – Howmanypagetableentriesdoweneedforone process?

• Problem:

– Pagetableisverylarge – Accesshastobefast,lookupforeverymemory reference – Wheredowestorethepagetable?

• Registers?
• Mainmemory?

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PageTables

• Pagetablesareimplementedasdatastructuresinmain

memory

• Mostprocessesdonotusethefull4GBaddressspace

– e.g.,0.1– 1MBtext,0.1– 10MBdata,0.1MBstack

• Weneedacompactrepresentationthatdoesnotwaste

space

– Butisstillveryfasttosearch

• Threebasicschemes

– Usedatastructuresthatadapttosparsity – Usedatastructureswhichonlyrepresentresidentpages – UseVMtechniquesforpagetables(detailslefttoextendedOS)

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Two levelPage Table

• 2nd –level

pagetables representing unmapped pagesarenot allocated

– Nullinthe top level pagetable

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Two levelTranslation Alternative:InvertedPageTable

PID VPN next PID VPN

• ffset

Index 1 2 3 4 5 6 F IPT:entryforeach frame

HashAnchorTable (HAT)

Hash ctrl

Alternative:InvertedPageTable

PID VPN next PID VPN

• ffset

Index 1 2 F 0x40C 0x40D F F

HashAnchorTable (HAT)

Hash ctrl 0x5 0x123 1 0x1A 0x40C 0x5 0x0 2 0x40C 0x123 ppn

• ffset

5

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InvertedPageTable(IPT)

• “Invertedpagetable”isanarrayofpage

numberssorted(indexed)byframenumber(it’s aframetable).

• Algorithm

– Computehashofpagenumber – Extractindexfromhashtable – Usethistoindexintoinvertedpagetable – MatchthePIDandpagenumberintheIPTentry – Ifmatch,usetheindexvalueasframe#for translation – Ifnomatch,getnextcandidateIPTentryfromchain field – IfNULLchainentry⇒ pagefault

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PropertiesofIPTs

• IPTgrowswithsizeofRAM,NOTvirtualaddressspace
• Frametableisneededanyway(forpagereplacement,

morelater)

• Needaseparatedatastructurefornon residentpages
• Savesavastamountofspace(especiallyon64 bit

systems)

• UsedinsomeIBMandHPworkstations

Given processes

• howmanypagetableswillthesystem

havefor

– ‘normal’pagetables – invertedpagetables?

AnotherlookatsharingF

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2 6 13 4 3 1 3 13 Proc1Address Space

Physical AddressSpace

7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 2 5 4 7 Page Table 7 6 5 3 1 15 14 13 12 11 10 9 8 4 2 1 2 7 Proc2Address Space Page Table

Two(ormore) processes runningthe sameprogram andsharing thetextsection

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• Problem:

– Eachvirtualmemoryreferencecancausetwo physicalmemoryaccesses

• Onetofetchthepagetableentry
• Onetofetch/storethedata

⇒Intolerableperformanceimpact!!

• Solution:

– High speedcacheforpagetableentries(PTEs)

• Calleda(TLB)
• Containsrecentlyusedpagetableentries
• Associative,high speedmemory,similartocachememory
• MaybeunderOScontrol(unlikememorycache)

VMImplementationIssue

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TLBoperation

On CPU hardware device!!! Data structure inmain memory

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TranslationLookasideBuffer

• Givenavirtualaddress,processorexaminesthe

TLB

• IfmatchingPTEfound(),theaddressis

translated

• Otherwise(),thepagenumberisused

toindextheprocess’spagetable

– IfPTcontainsavalidentry,reloadTLBandrestart – Otherwise,(pagefault)checkifpageisondisk

• Ifondisk,swapitin
• Otherwise,allocateanewpageorraiseanexception

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TLBproperties

• Pagetableis(logically)anarrayofframe

numbers

• TLBholdsa(recentlyused)subsetofPTentries

– EachTLBentrymustbeidentified(tagged)withthe page#ittranslates – Accessisbyassociativelookup:

• AllTLBentries’tagsareconcurrentlycomparedtothepage#
• TLBisassociative(orcontent addressable)memory

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TLBproperties

• TLBmayormaynotbeunderdirectOScontrol

– Hardware loadedTLB

• Onmiss,hardwareperformsPTlookupandreloadsTLB
• Example:Pentium

– Software loadedTLB

• Onmiss,hardwaregeneratesaTLBmissexception,and

exceptionhandlerreloadsTLB

• Example:MIPS
• TLBsize:typically64 128entries
• CanhaveseparateTLBsforinstructionfetch

anddataaccess

• TLBscanalsobeusedwithinvertedpagetables

(andothers)

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TLBandcontextswitching

• TLBisasharedpieceofhardware
• Pagetablesareper process(addressspace)
• TLBentriesare

– OncontextswitchneedtotheTLB(invalidate allentries)

• highcontext switchingoverhead(Intelx86)

– tagentrieswith(ASID)

• calleda
• used(insomeform)onallmodernarchitectures
• TLBentry:ASID,page#,frame#,validandwrite protect

bits

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TLBeffect

• WithoutTLB

– Averagenumberofphysicalmemory referencespervirtualreference

=2

• WithTLB(assume99%hitratio)

– Averagenumberofphysicalmemory referencespervirtualreference

=.99*1+0.01*2 =1.01

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Recap SimplifiedComponentsof VMSystem

1 2 3 CPU FramePool

1 3 2 TLB

VirtualAddressSpaces (3processes) PageTablesfor3 processes FrameTable PhysicalMemory 39

MIPSR3000TLB

• N=Notcacheable
• D=Dirty=Writeprotect
• G=Global(ignoreASID

inlookup)

• V=validbit
• 64TLBentries
• Accessedviasoftwarethrough

Cooprocessor0registers

– EntryHiandEntryLo

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R3000Address SpaceLayout

• kuseg:

– 2gigabytes – TLBtranslated(mapped) – Cacheable(dependingon‘N’bit) – user modeandkernelmode accessible – Pagesizeis4K

kseg0 kuseg 0x00000000 0x80000000 kseg1 kseg2 0xA0000000 0xC0000000 0xFFFFFFFF

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R3000Address SpaceLayout

– Switchingprocesses switchesthetranslation (pagetable)forkuseg kseg0 Proc3 kuseg 0x00000000 0x80000000 kseg1 kseg2 0xA0000000 0xC0000000 0xFFFFFFFF Proc2 kuseg Proc1 kuseg

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R3000Address SpaceLayout

• kseg0:

– 512megabytes – Fixedtranslationwindowto physicalmemory

• 0x80000000 0x9fffffffvirtual=

0x00000000 0x1fffffffphysical

• TLBnotused

– Cacheable – Onlykernel modeaccessible – Usuallywherethekernelcodeis placed

kseg0 kuseg

• kseg1

kseg2

• PhysicalMemory

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R3000Address SpaceLayout

• kseg1:

– 512megabytes – Fixedtranslationwindowto physicalmemory

• 0xa0000000 0xbfffffffvirtual=

0x00000000 0x1fffffffphysical

• TLBnotused

– "#$cacheable – Onlykernel modeaccessible – Wheredevicesareaccessed(and bootROM)

kseg0 kuseg

• kseg1

kseg2

• PhysicalMemory

8

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R3000Address SpaceLayout

• kseg2:

– 1024megabytes – TLBtranslated(mapped) – Cacheable

• Dependingonthe‘N’ bit

– Onlykernel modeaccessible – Canbeusedtostorethevirtual lineararraypagetable

kseg0 kuseg

• kseg1

kseg2