Memory�Management�Unit Virtual�Memory The�position�and�function�of�the�MMU 1 2 Typical�Address� Virtual�Address� Virtual�Address� Paging Space 15 Space 15 Space�Layout 14 14 Kernel 13 13 • Virtual�Memory • Physical�Memory • Stack�region�is�at�top,� 12 12 – Divided�into�equal and�can�grow�down 11 – Divided�into� 11 Stack sized� ����� • Heap�has�free�space�to� 10 equal sized� 10 – A� ������� is�a� Shared� grow�up translation�between� ������ 9 9 Libraries • A�page�and�a�frame 8 8 • Text�is�typically�read only • A�page�and�null 7 1 7 7 • Kernel�is�in�a�reserved,� BSS – Mappings�defined�at� 6 12 6 6 protected,�shared�region runtime (heap) • They�can�change 5 10 5 5 • 0 th�page�typically�not� – Address�space�can� 4 4 Data 4 used,�why? have�holes 3 2 3 3 – Process�does�not� 2 2 2 have�to�be� Text contiguous�in� Physical�Address� 1 3 1 1 (Code) physical�memory Space 3 4 0 11 0 0 Proc�1�Address� Proc�2�Address� ������������������������ :� Virtual�Address� Space Space logically�present 15 15 15 Space �������������������� :�Not� Currently� 14 14 14 running mapped,�data�on�disk 13 13 13 • A�process�may� 12 12 12 Physical� be�only�partially� Address�Space 4 11 11 11 resident 14 6 2 10 10 10 15 – Allows�OS�to� 2 4 9 9 9 14 14 store�individual� 10 13 8 8 8 2 3 pages�on�disk 4 7 1 7 7 15 1 Disk – Saves�memory� 1 6 15 6 6 for�infrequently� 2 Disk 5 5 5 used�data�&�code 3 4 4 4 Memory� • What�happens�if� 13 3 5 3 3 Access we�access�non 2 2 2 resident� Physical�Address� 1 3 1 1 memory? Space 5 6 0 13 0 0 1
Virtual�Address� Page�Faults Space 15 6 Page� 14 • Referencing�an�invalid�page�triggers�a�page�fault Table 13 0 • An�exception�handled�by�the�OS • Page�table�for� 12 • Broadly,�two�standard�page�fault�types resident�part�of� 11 – Illegal�Address�(protection�error) address�space� 10 • Signal�or�kill�the�process 9 – Page�not�resident • Get�an�empty�frame 8 • Load�page�from�disk 7 1 7 • Update�page�(translation)�table�(enter�frame�#,�set�valid�bit,�etc.) 6 15 6 • Restart�the�faulting�instruction 5 5 3 5 4 4 4 3 5 1 3 2 2 2 Physical� 1 3 7 1 7 Address�Space 8 0 13 0 Shared�Pages • Private�code�and�data • Shared�code • Note:�Some�implementations�store�disk� block�numbers�of�non resident�pages�in� – Each�process�has�own� – Single�copy�of�code� copy�of�code�and�data shared�between�all� the�page�table�(with�valid�bit� ����� ) processes�executing�it – Code�and�data�can� appear�anywhere�in� – Code�must�not�be�self� the�address�space modifying – Code�must�appear�at� same�address�in�all� processes 9 10 Proc�1�Address� Proc�2�Address� Space Space Page�Table�Structure 15 15 14 14 • Page�table�is�(logically)�an�array�of� 0 13 13 5 5 12 12 frame�numbers Physical� Address�Space 11 11 – Index�by�page�number 2 10 10 6 • Each�page table�entry�(PTE)�also�has� 9 9 13 8 8 other�bits 4 7 7 Two�(or�more)� 3 6 6 processes� 1 5 5 running�the� 3 same�program� 4 4 4 4 and�sharing�� 13 1 3 3 the�text�section 7 2 2 7 7 Page� Page� Page� 2 1 1 2 2 Table Table Table 11 12 0 0 2
PTE�bits Address�Translation • Present/Absent�bit – Also�called� ����������� it�indicates�a�valid�mapping�for�the�page • Every�(virtual)�memory�address�issued�by� • Modified�bit the�CPU�must�be�translated�to�physical� – Also�called� ����������� it�indicates�the�page�may�have�been� modified�in�memory memory • Reference�bit – Every� ���� and�every� ����� instruction – Indicates�the�page�has�been�accessed • Protection�bits – Every�instruction�fetch – Read�permission,�Write�permission,�Execute�permission • Need�Translation�Hardware – Or�combinations�of�the�above • Caching�bit • In�paging�system,�translation�involves� – Use�to�indicate�processor�should�bypass�the�cache�when� replace�page�number�with�a�frame�number accessing�memory • Example:�to�access�device�registers�or�memory 13 14 Page�tables�(recap) virtual�memory Page�Tables virtual�and�physical�mem�chopped�up�in�pages • Assume�we�have • ��������������������� – 32 bit�virtual�address�(4�Gbyte�address�space) ��������� – 4�KByte�page�size • ���������������������������� – How�many�page�table�entries�do�we�need�for�one� ������ process? ����������������������������� �������������������� � ������ ���������������������������� ��!��������������������� ������ ����������������������������� � � � � ���������� 18 3
Page�Tables Page�Tables • Assume�we�have • Page�tables�are�implemented�as�data�structures�in�main� memory – 64 bit�virtual�address�(humungous address�space) – 4�KByte�page�size • Most�processes�do�not�use�the�full�4GB�address�space – How�many�page�table�entries�do�we�need�for�one� – e.g.,�0.1�– 1�MB�text,�0.1�– 10�MB�data,�0.1�MB�stack process? • We�need�a�compact�representation�that�does�not�waste� • Problem: space – Page�table�is�very�large – But�is�still�very�fast�to�search • Three�basic�schemes – Access�has�to�be�fast,�lookup�for�every�memory� reference – Use�data�structures�that�adapt�to�sparsity – Where�do�we�store�the�page�table? – Use�data�structures�which�only�represent�resident�pages • Registers? – Use�VM�techniques�for�page�tables�(details�left�to�extended�OS) • Main�memory? 19 20 Two level�Page� Two level�Translation Table • 2 nd –level� page�tables� representing� unmapped� pages�are�not� allocated – Null�in�the� top level� page�table 21 22 Alternative:�Inverted�Page�Table Alternative:�Inverted�Page�Table PID VPN offset PID VPN offset 0 0x5 0x123 Index PID VPN ctrl next Index PID VPN ctrl next 0 0 Hash�Anchor�Table Hash�Anchor�Table (HAT) (HAT) 1 1 1 0x1A 0x40C 2 2 Hash Hash 3 F 4 0x40C 0 0x5 0x0 5 0x40D 2 6 F F F ppn offset IPT:�entry�for�each� �������� frame 0x40C 0x123 4
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