Measurement Considerations for Evaluating BTI Effects in SiC MOSFETs - - PowerPoint PPT Presentation

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The Nation’s Premier Laboratory for Land Forces

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The Nation’s Premier Laboratory for Land Forces

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Measurement Considerations for Evaluating BTI Effects in SiC MOSFETs

Daniel Habersat Aivars Lelis (TL), Ronald Green

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Background

 Switching oxide trap, direct tunneling mechanism.  Defect is an E′ center (hole trap), associated with O vacancy  Similar behavior as seen with ionizing radiation

• n Si/SiO2.

 Presence of defect confirmed in SiC MOS  Bias and temperature convert neutral Si-dimer to active E′ center  Same as in Si/SiO2 PBTI ? Meta-stable high-temperature electron trap ? Counteracting mobile ion or polarization charge ? Indirect tunneling via interface traps

EFM EV EC EFS

SiO2 SiC

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5 10 15 3 3.5 4 4.5 Drain Current [mA] Gate-Source Bias [V] pre-stress stress Vendor A 2.9 MV/s

Typical PBS Response (simplified)

• Representative pre- and

post-stress ID-VGS

• Charge-trapping-like

response:

• PBS shifts curves

positively

• NBS shifts curves

negatively

• Roughly linear-with-log

time

• Generally nonpermanent

and reversible … BUT:

+ stress 1 2 1 2 10⁻⁶ 10⁻³ 10⁰ 10³ 10⁶ 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 Threshold Voltage [V] Stress Time [s] Vendor B Vendor A

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tM [s] 10-6 10-4 10-2 100 102 104

Experimental: Measurement Considerations

VT drift results are highly dependent on the delay between stress and measurement!

0.1 0.2 0.3 0.4 0.5 0.6 0.7 VT Drift [V] tS [s] 10-6 10-4 10-2 100 102 104 Pre-stress Stress Recover 5 10 15 20 VGS [V] Time

Recovery during delay appears to be the dominant reason for differences between measurements.

VGS = +15 V VGS = +2 V

Data from Vendor A COTS Increasing tS ΔVT as measured normally 2 μs measurement time 2 s measurement time

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HTGB Qualification Specifications

• AEC – Q101 Stress Test Qualification for Automotive Grade Discrete

Semiconductors

• JEDEC JESD-22 A108E Reliability Test Methods for Packaged Devices
• MIL-STD-750 Test Methods for Semiconductors

AEC Q101 – Rev D JESD-22 A108E “Electrical testing shall be completed as soon as possible and no longer than 96 hours after removal of bias from devices.”

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The Nation’s Premier Laboratory for Land Forces Industry Needs and Existing HTGB Test Method for SiC MOSFETs

• Industry requires large-scale test

systems for qualification testing and screening.

• Many SiC manufacturers qualify

devices to Q101 automotive standard.

• Devices stressed in parallel for 1000

hours.

• Biased cool down to 25 °C (1 min. bias

interruption allowed per JESD22 - A108C for moving devices to test area).

• Bias interruption times generally >> 1

minute in practice.

• Devices can remain unbiased for up

to 96 hrs. prior to electrical testing per JESD22 – A108C without any requirement to reapply bias stress.

• JESD22-A108C does have an additional

stress requirement when devices have remained unbiased for longer than 96

• hrs. prior to electrical testing.
• Serial testing leads to variation in

interrupt/delay times

AEC-Q101- Rev D1

• Sept. 6, 2013

Example of HTGB test procedure used by manufacturers for qualification:

Type Test Description Condition

Device HTRB High Temperature Reverse Bias 1000 hr. HTGB High Temperature Gate Bias 1000 hr. HTOL High Temperature Operating Life 1000 hr.

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Gate Biasing Sequence

Pre-stress Stress Interrupt Reapply (1) (2) (3) (4) Gate-Source Bias Time [arb]

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5 10 15 3 3.5 4 4.5 Drain Current [mA] Gate-Source Bias [V] pre-stress interrupt reapply stress Vendor A 2.9 MV/s

Sequential Charging of the Oxide Traps

• Tunneling fronts move into

the oxide

• Bias determines resultant

charge state

• Time determines penetration

depth (log t)

• Superposition of multiple

fronts

Static Oxide Bulk Measurement Trap Occupation Interface + stress interrupt reapply 1 2 2 3 3 4 1 2 3 4 Gate-Source Bias Time [arb] Prestress (1) Stress (2) Interrupt (3) Reapply (4)

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Pre-stress Biasing

Pre-stress Stress Interrupt Reapply (1) (2) (3) (4) Gate-Source Bias Time [arb]

Pre-stress

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Pre-stress bias (PBS)

10⁻⁶ 10⁻³ 10⁰ 10³ 3 3.5 4 4.5 5 5.5 Threshold Voltage [V] Positive Bias Stress Time [s] 0 V pre / +25 V stress –5 V pre / +25 V stress –10 V pre / +25 V stress Vendor B

• Identical stressing

parameters

• Pre-stress time for roughly

the same time as the stress (2×104 s)

• Three pre-stress biases:

0V, -5V, and -10V (saturated by -15V)

• More negative biasing

causes:

• Negative shift in original

VT

• Reduced VT for first

100s or so

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Pre-stress bias (NBS)

• Identical stressing

parameters

• Pre-stress time for roughly

the same time as the stress (2×104 s)

• Three pre-stress biases:

0V, +5V, and +10V (no saturation seen to +25V)

• More positive biasing

causes:

• Positive shift in original

VT

• No significant changes

in post-NBS VT values

10⁻⁶ 10⁻³ 10⁰ 10³ 3 3.5 4 4.5 5 5.5 Threshold Voltage [V] Negative Bias Stress Time [s] +10 V pre / –15 V stress +5 V pre / –15 V stress 0 V pre / –15 V stress Vendor B

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Pre-stress Bias (Drift)

• Interpretation of results usually

based on drift values

• PBS Drift:
• Early times appear identical
• Dispersion in final drift

values based on pre-bias magnitude (larger pre-bias -> larger drift)

• 0V device seems to have

lower density of switching

• xide traps
• NBS Drift:
• Drifts are parallel
• Magnitude of drift correlates

with pre-bias magnitude

• 0V device seems to have a

lower density of fast interface states

10⁻⁶ 10⁻³ 10⁰ 10³

• 2
• 1.5
• 1
• 0.5

0.5 1 1.5 2 Threshold Voltage Drift [V] Stress Time [s]

–10 V pre / +25 V stress 0 V pre / –15 V stress –5 V pre / +25 V stress +5 V pre / –15 V stress 0 V pre / +25 V stress +10 V pre / –15 V stress

Vendor B

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Sweep Speed

Pre-stress Stress Interrupt Reapply (1) (2) (3) (4) Gate-Source Bias Time [arb]

Sweep Speed

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Sweep Speed (PBS)

10⁻⁶ 10⁻³ 10⁰ 10³ 2.5 3 3.5 4 4.5 5 Threshold Voltage [V] Stress Time [s] 2 x 10⁶ (5 µs) 2 x 10⁵ (50 µs) 2 x 10⁴ (500 µs) 4 x 10³ (2.5 ms)

Slew Rate [V/s]

Vendor A

• Already know that faster

sweeps  larger drift

• With negative pre-stress

bias, reference VT was independent of slew rate (???)

• Faster sweep  capture of

more near-interface states

• Growth of VT (i.e. drift) is

roughly parallel for longer times

• As stress’ tunneling

front moves deeper, measurement speed matters less

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Sweep Speed (NBS)

10⁻⁶ 10⁻³ 10⁰ 10³ 2.5 3 3.5 4 4.5 5 Threshold Voltage [V] Stress Time [s] 4 x 10³ (2.5 ms) 2 x 10⁴ (500 µs) 2 x 10⁵ (50 µs) 2 x 10⁶ (5 µs)

Slew Rate [V/s]

Vendor A

• Contrast NBS to PBS:
• Reference VT IS slew-rate

dependent

• Drift rate (slope) is also slew-

rate dependent

• Why are the responses so

different between PBS and NBS?

• ¯\_(ツ)_/¯
• Under investigation

? Combination of interactions between pre-stress bias, stress bias, and portions of the IV sweep before and after the VT measurement ? Initial response to NBS is very rapid, while PBS tends to be slower… ? PBS: (Np/nPp/nPp/…) ? NBS: (Pn/pNn/pNn/…)

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Interrupt Time

Pre-stress Stress Reapply (1) (2) (3) Gate-Source Bias Time [arb]

Interrupt

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Interrupt Time

• Study the effects of

interrupt time, for relatively “long” stresses

• Drift between the two I-V

curves immediately before and after the bias interruption

• With interrupt time <<

stress time, we get a recovery in the VT drift that is independent of stress time

• Only affecting the traps

nearest to the interface

• Deeper traps remain

undisturbed

5 10 15 3 3.5 4 4.5 Drain Current [mA] Gate-Source Bias [V] pre-stress interrupt stress Vendor A 2.9 MV/s + stress interrupt 1 2 2 3 1 2 3 10⁻⁶ 10⁻³ 10⁰ 10³

• 0.8
• 0.7
• 0.6
• 0.5
• 0.4
• 0.3
• 0.2
• 0.1

Threshold Voltage Drift [V] Interrupt Time [s] 3.2 x 10¹ 1.0 x 10² 3.2 x 10² 1.0 x 10³ 3.2 x 10³

Stress Time [s]: Vendor A 1.3 MV/s

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Reapply Time

Pre-stress Stress Interrupt Reapply (1) (2) (3) (4) Gate-Source Bias Time [arb]

Reapply

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5 10 15 3 3.5 4 4.5 Drain Current [mA] Gate-Source Bias [V] pre-stress interrupt reapply stress Vendor A 2.9 MV/s

Reapply Time

• 32s +25V stress
• Short duration interrupts

cause some loss of VT drift

• Longer interruptions can

cause almost ALL drift to recover

• Highlighted scenario:
• 32s stress, 10s interrupt
• No reapply  nearly

total recovery of VT

• 0.3s reapply  nearly

full VT drift observed

10⁻⁶ 10⁻³ 10⁰ 10³ 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Threshold Voltage Drift [V] Reapply Time [s] 1 x 10⁻⁴ 1 x 10⁻³ 1 x 10⁻² 1 x 10⁻¹ 1 x 10⁰ 1 x 10¹ Vendor B 1.3 MV/s

Interrupt Time [s]:

+ stress interrupt reapply 1 2 2 3 3 4 1 2 3 4

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Universal Drift Again

• As shown last

year: square of reapply time, divided by interrupt time, gives a reasonable correlation with fractional VT drift

• Specific fraction

appears to have a sweep rate component (???)

• Reapply time

much shorter than interrupt time can restore most of the drift

10⁻¹² 10⁻⁹ 10⁻⁶ 10⁻³ 10⁰ 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fractional VT Drift tR

2/tI [s]

Vendor B 1.3 MV/s

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High Temperature Bias Stressing, Interruption, and Reapplication

10⁻¹⁸ 10⁻¹⁵ 10⁻¹² 10⁻⁹ 10⁻⁶ 10⁻³ 10⁰ 10³ 10⁶ 10⁹

• 0.2

0.2 0.4 0.6 0.8 1 1.2 Fractional VT Drift tR2 / tI [s] 25°C 175°C

• Room temperature

analysis  reasonable agreement with high temperature data

• Yes, activation is
• ccurring and

changing the active trap density, but the basic tunneling mechanism behaves the same

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Significance / Take-Aways

• Establish a pre-stress conditioning protocol (e.g., bias at −10 V

for 1 hour). A pre-stress that opposes the polarity of the stress will show the most meaningful results.

• A consistently applied pre-stress conditioning will provide a

sound basis for evaluating drift between devices or tests of the same device. Otherwise, you will need to look at bothVT and VT drift.

• Make your measurements as quickly (and consistently) as

possible.

• Minimize bias interruptions and delays between stressing and

measuring.

• An estimate of the VT drift lost due to a bias interruption after a

long-term stress could be estimated by conducting a shorter stress measurement with the same interrupt time (as long as the new stress time is still greater than the interrupt time).

• If there is a bias interruption, even for a short time, re-establish

the stress bias and hold briefly, immediately before measuring.

• Perform measurements at the same temperature as the
• stressing. (This will both reduce any bias interruptions as well as

prevent thermally-induced relaxation of trapped charge.)