MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - PowerPoint PPT Presentation

MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture

Overview ¨ Announcement ¤ Homework 4 submission deadline: Nov. 6 th ¨ This and the following lectures ¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies

Recall: Address Translation ¨ Exploit locality to reduce address translation time ¤ Offset bits are copied from virtual address Virtual Address Physical Memory Virtual Page No offset Page Frame 0 Page Frame 1 Page frame No offset Page Frame 2 Physical Address … Page Frame N-1

Recall: Address Translation ¨ Exploit locality to reduce address translation time ¤ OS maintains the page table for address translation Virtual Address Physical Memory Virtual Page No offset Page Frame 0 Page Frame 1 Page frame No offset Page Frame 2 Physical Address … Page Frame N-1 Page Table

Recall: Translation Lookaside Buffer ¨ Exploit locality to reduce address translation time ¤ Keep recent translation in a buffer for future references 0 Virtual 1 TLB Address Physical Memory 0 Virtual Page No offset Page 1 Frame 0 Page Frame 1 Page frame No offset Page Frame 2 Physical Address … Page Frame N-1 Page Table

TLB in Memory Hierarchy ¨ On a TLB miss, is the page loaded in memory? ¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault n Takes 1,000,000’s cycles to load the page and update TLB hit PA VA miss Processor TLB Main Cache Core Lookup Memory hit Data

TLB in Memory Hierarchy ¨ On a TLB miss, is the page loaded in memory? ¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault n Takes 1,000,000’s cycles to load the page and update TLB hit PA VA miss Processor TLB Main Cache Core Lookup Memory miss hit Translaltion Data

TLB in Memory Hierarchy ¨ On a TLB miss, is the page loaded in memory? ¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault n Takes 1,000,000’s cycles to load the page and update TLB Physically indexed, physically tagged: TLB on critical path! hit PA VA miss Processor TLB Main Cache Core Lookup Memory miss hit Translaltion Data

Physically Indexed Caches ¨ Problem: increased critical path due to sequential access to TLB and cache Virtual Page No Page Offset TLB Physical Frame Page Offset

Physically Indexed Caches ¨ Problem: increased critical path due to sequential access to TLB and cache Virtual Page No Page Offset TLB Physical Frame Page Offset Tag Index Byte Tag Array Data Array = Data Block hit/miss*

Physically Indexed Caches ¨ Problem: increased critical path due to sequential access to TLB and cache Virtual Page No Page Offset Observation: lower address TLB bits (page offset) are not translated Physical Frame Page Offset Tag Index Byte Tag Array Data Array = Data Block hit/miss*

Virtually Indexed Caches ¨ Idea: Index into cache in parallel with page number translation in TLB Virtual Page No Page Offset Index Byte TLB Tag Array Data Array Tag Data Block = hit/miss*

Virtually Indexed Caches ¨ Idea: Index into cache in parallel with page number translation in TLB what if the page offset is not Virtual Page No Page Offset equal to index+byte? Index Byte TLB Tag Array Data Array Tag Data Block = hit/miss*

Main Memory

Computer System Overview ¨ DRAM technology is commonly used for main memory

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU Memory

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU ¨ SRAM is used for caches ¨ DRAM is used for main memory ¨ DRAM is accessed Memory on a TLB or last level cache miss

Static vs. Dynamic RAM Static RAM (SRAM) Dynamic RAM (DRAM) bitline bitline bitline wordline wordline

Static vs. Dynamic RAM Static RAM (SRAM) Dynamic RAM (DRAM) ¨ Fast and leaky ¨ Dense and slow ¤ 6 transistors per bit ¤ 1 transistor per bit ¤ Normal CMOS Tech. ¤ Special DRAM process ¨ Static volatile ¨ Dynamic volatile ¤ Retain data as long as ¤ Periodic refreshing is powered on required to retain data

DRAM Organization ¨ DRAM array is organized as rows � columns

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline decoder

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline decoder Sense Amplifier row buffer

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline decoder Sense Amplifier row buffer multiplexer Data Block

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline Row Address decoder Sense Amplifier row buffer multiplexer Column Address Data Block

DRAM Organization ¨ DRAM array is organized as rows � columns bitline wordline Row Address decoder Sense Amplifier row buffer multiplexer All reads and writes are Column performed through the Address row buffer Data Block

DRAM Row Buffer ¨ All reads and writes are performed through RB DRAM Cell Row Access Data Array Strobe (RAS) Column Access Row Buffer (RB) Strobe DRAM (CAS) Sense Amp.

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense Reading a zero Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 0 Reading a zero ? Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 0 1 Reading a zero ? ? Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 0 Reading a one ?

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 V/2 0 1 Reading a one ? ?

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 V/2 V/2 - � 1 0 1 Reading a one V ? ?