MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - - PowerPoint PPT Presentation

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Sep 10, 2023 356 likes •714 views

MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Homework 4 submission deadline: Nov. 6 th This and the following lectures

SLIDE 1

MAIN MEMORY SYSTEM

CS/ECE 6810: Computer Architecture

Mahdi Nazm Bojnordi

Assistant Professor School of Computing University of Utah

SLIDE 2

Overview

¨ Announcement

¤ Homework 4 submission deadline: Nov. 6th

¨ This and the following lectures

¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies

SLIDE 3

Recall: Address Translation

¨ Exploit locality to reduce address translation time

¤ Offset bits are copied from virtual address

Physical Memory

Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …

Virtual Address Physical Address

ffset
ffset

Virtual Page No Page frame No

SLIDE 4

Recall: Address Translation

¨ Exploit locality to reduce address translation time

¤ OS maintains the page table for address translation

Physical Memory

Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …

Virtual Address Physical Address

ffset
ffset

Virtual Page No Page frame No

Page Table

SLIDE 5

Recall: Translation Lookaside Buffer

¨ Exploit locality to reduce address translation time

¤ Keep recent translation in a buffer for future references

Physical Memory

Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …

Virtual Address Physical Address

ffset
ffset

Virtual Page No Page frame No

Page Table

1 1

TLB

SLIDE 6

TLB in Memory Hierarchy

¨ On a TLB miss, is the page loaded in memory?

¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault

n Takes 1,000,000’s cycles to load the page and update TLB

Processor Core TLB Lookup Cache Main Memory VA hit PA miss Data hit

SLIDE 7

TLB in Memory Hierarchy

¨ On a TLB miss, is the page loaded in memory?

¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault

n Takes 1,000,000’s cycles to load the page and update TLB

Processor Core TLB Lookup Cache Main Memory VA hit PA miss Translaltion miss Data hit

SLIDE 8

TLB in Memory Hierarchy

¨ On a TLB miss, is the page loaded in memory?

¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault

n Takes 1,000,000’s cycles to load the page and update TLB

Processor Core TLB Lookup Cache Main Memory VA hit PA miss Translaltion miss Data hit Physically indexed, physically tagged: TLB on critical path!

SLIDE 9

Physically Indexed Caches

¨ Problem: increased critical path due to sequential

access to TLB and cache

Virtual Page No Page Offset TLB Physical Frame Page Offset

SLIDE 10

Physically Indexed Caches

¨ Problem: increased critical path due to sequential

access to TLB and cache

Virtual Page No Page Offset TLB Physical Frame Page Offset Tag Array Data Array = Data Block hit/miss* Tag Index Byte

SLIDE 11

Physically Indexed Caches

¨ Problem: increased critical path due to sequential

access to TLB and cache

Virtual Page No Page Offset TLB Physical Frame Page Offset Tag Array Data Array = Data Block hit/miss* Tag Index Byte

Observation: lower address bits (page offset) are not translated

SLIDE 12

Virtually Indexed Caches

¨ Idea: Index into cache in parallel with page number

translation in TLB

Virtual Page No Page Offset TLB Tag Array Data Array = Data Block hit/miss* Tag Index Byte

SLIDE 13

Virtually Indexed Caches

¨ Idea: Index into cache in parallel with page number

translation in TLB

Virtual Page No Page Offset TLB Tag Array Data Array = Data Block hit/miss* Tag Index Byte

what if the page offset is not equal to index+byte?

SLIDE 14

Main Memory

SLIDE 15

Computer System Overview

¨ DRAM technology is commonly used for main

memory

SLIDE 16

Computer System Overview

¨ DRAM technology is commonly used for main

memory

CPU

SLIDE 17

Computer System Overview

¨ DRAM technology is commonly used for main

memory

CPU Memory

SLIDE 18

Computer System Overview

¨ DRAM technology is commonly used for main

memory

CPU Memory

¨ SRAM is used for

caches

¨ DRAM is used for

main memory

¨ DRAM is accessed

n a TLB or last

level cache miss

SLIDE 19

Static vs. Dynamic RAM

Static RAM (SRAM) Dynamic RAM (DRAM)

wordline bitline bitline wordline bitline

SLIDE 20

Static vs. Dynamic RAM

¨ Fast and leaky

¤ 6 transistors per bit ¤ Normal CMOS Tech.

¨ Static volatile

¤ Retain data as long as

powered on

¨ Dense and slow

¤ 1 transistor per bit ¤ Special DRAM process

¨ Dynamic volatile

¤ Periodic refreshing is

required to retain data

Static RAM (SRAM) Dynamic RAM (DRAM)

SLIDE 21

DRAM Organization

¨ DRAM array is organized as rowscolumns

SLIDE 22

DRAM Organization

¨ DRAM array is organized as rowscolumns

wordline bitline

SLIDE 23

DRAM Organization

¨ DRAM array is organized as rowscolumns

decoder

wordline bitline

SLIDE 24

DRAM Organization

¨ DRAM array is organized as rowscolumns

decoder Sense Amplifier row buffer

wordline bitline

SLIDE 25

DRAM Organization

¨ DRAM array is organized as rowscolumns

decoder Sense Amplifier row buffer

wordline bitline

Data Block multiplexer

SLIDE 26

DRAM Organization

¨ DRAM array is organized as rowscolumns

decoder Row Address Column Address Sense Amplifier row buffer

wordline bitline

Data Block multiplexer

SLIDE 27

DRAM Organization

¨ DRAM array is organized as rowscolumns

decoder Row Address Column Address Sense Amplifier row buffer

wordline bitline

Data Block multiplexer All reads and writes are performed through the row buffer

SLIDE 28

DRAM Row Buffer

¨ All reads and writes are performed through RB

Data Array Row Buffer (RB) DRAM Cell DRAM Sense Amp. Row Access Strobe (RAS) Column Access Strobe (CAS)

SLIDE 29