M ULTICORE H ARDWARE S HARED R ESOURCES : U NDERSTANDING OF THE S - - PowerPoint PPT Presentation
C ONTENTION IN M ULTICORE H ARDWARE S HARED R ESOURCES : U NDERSTANDING OF THE S TATE OF THE A RT Gabriel Fernandez 1 , Jaume Abella 2 , Eduardo Quiones 2 , Christine Rochange 3 , Tullio Vardanega 4 and Francisco J. Cazorla 2,4 1 2 3 5 4 14
Gabriel Fernandez1, Jaume Abella2, Eduardo Quiñones2, Christine Rochange3, Tullio Vardanega4 and Francisco J. Cazorla2,4
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14th International Workshop on Worst‐Case Execution Time Analysis (WCET 2014)
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– Allow higher “guaranteed performance”
– Interference on execution time and WCET due to contention in the access to HW shared resources
studied by the research community
– Different approaches taken to contention
– The solutions space is difficult to fully understand
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techniques
– Identifying ‘families’ of techniques – Singling out representative works for each class
– Seeking overlaps and gaps with others – Understanding assumptions and challenges of use – Gaging confidence in WCET bounds and assurance guarantees for industrial use
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System Centric Time Analysis Frameworks Task Assignment and Scheduling Handling Contention WCET Centric Contention aware Contention
Joint Analysis Independent Analysis Architecture Centric COTS Centric Bottom‐up / Top‐down Idealistic‐innovative / Practical‐pragmatic
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System Centric Time Analysis Frameworks Task Assignment and Scheduling Handling Contention Contention aware Contention
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– SW on core suffers no parallel contention
– Provide worst‐case access timing bounds – Contention captured compositionally: off‐chip contention in the presence of co‐runners
– Co‐running tasks do not affect one another’s execution time – Worst‐case alignment of the requests in the TDMA
– Co‐running tasks do affect one another’s execution time – Focus on deriving bounds for the number of accesses per task in a given period of time
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– The WCET of all tasks is given in input
made on task mapping and on scheduling
– Escape circularity in the mutual dependence between WCET analysis and schedulability analysis
– Focus on the shared last‐level cache – Benefit from HW techniques for cache partitioning
– Assume partitioned scheduling and augment assignment with colouring
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Handling Contention WCET Centric Joint Analysis Independent Analysis
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used to derive WCETs (IPET method)
– Worst‐case memory instruction latencies – Worst‐case number of L2 cache misses
– Contextual
analysis time ➙ joint analysis
– Universal
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– Iterative computation
– Timed automata + model checking
low‐ level analysis Task A low‐ level analysis Task A low‐ level analysis Task B low‐ level analysis Task B low‐ level analysis Task C low‐ level analysis Task C
analysis of possible interferences analysis of possible interferences tasks schedule
WCET
private resources shared resources
show: WCET(A) < x
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– Independent of task assignment and scheduling
– To derive worst‐case latencies and worst‐case behaviours – Examples include
tasks
case latencies
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Handling Contention Architecture Centric
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hardware shared resources
– TTA (<‘00), PRET (’06), CompSOC (‘09), MERASA (‘07), …
– WCET estimates
workloads its WCET estimate does not
– Execution time
reservation’ performance degradation
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hardware shared resources
– Indirectly: bandwidth guarantees – Directly: access time guarantees
– Stateless (e.g bus): access policy – Stateful (e.g. cache): partition to prevent task interaction
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Handling Contention COTS Centric
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multicores
– No assumptions can be made – Analyze hardware shared resources – Analyze their impact on execution time – Bounds derived by ad‐hoc experiments
shared resources
– The way they challenge timing analyzability
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– One shared resource, blocking and no split – Program broken down into superblocks with resource usage bounds per block – Dynamic arbiters
tightened but it is no longer time composable
– Static task‐to‐CPU assignment determines opponents
technique to avoid exploring the space of all possible contentions
the purpose
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Independent analysis Joint analysis
arbitration of shared resources
schedule known Independent analysis Joint analysis
estimation of contention)
explosion)
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– Applies to all hardware designs ;‐) – Cache partitioning mechanisms: won battle – Proposed changes are ‘simple’
– Design hardware that prevents appearance of TA
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controlled contention
– Not fully adopted!
– Build confidence arguments in accordance with requirements and practices of the application domain – How safety assurance relate to stipulating bounds
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needed
– Do they form a consistent picture from which a user can choose sensibly?
– Question for the audience
performance
– First negatively affects the second – Not possible in the single‐core sense compositional
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Work mainly funded by …
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