M ethodologies for Reducing ULP Device Power Consumption Dr. Ivan - - PowerPoint PPT Presentation

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Sep 23, 2022 387 likes •631 views

M ethodologies for Reducing ULP Device Power Consumption Dr. Ivan OConnell, & Donnacha ORiordan, M icroelectronic Circuis Centre Ireland (M CCI), Tyndall Wednesday 30 th M ay 2018 Energy Harvesting Source: Lorandt Foelkel, Energy

SLIDE 1

M ethodologies for Reducing ULP Device Power Consumption

Dr. Ivan O’Connell, & Donnacha O’Riordan,

M icroelectronic Circuis Centre Ireland (M CCI), Tyndall Wednesday 30th M ay 2018

SLIDE 2

Energy Harvesting

Source: Lorandt Foelkel, “Energy Harvesting Seminar," Wurth Elektronik eiSos, 2013

SLIDE 3

Address the “Energy Gap”
Designers always look for ways to reduce unwanted components of power

consumption – architecting the design in a fashion which includes low power techniques – adopting a process which can reduce the consumption

Always done at the expense of performance, reliability, chip area, or several of

these – one has to reach a compromise between power, performance, and cost

M otivation

SLIDE 4

Battery Powered Systems – Phones

– M obile revolution has really driven need for low power design

High-Performance Systems – Server Farms

– Cost of removing the unused energy  Heat – Reliability

– Deploy and forget devices – Cost of transmitting data  move processing being done at the edge

Ultra Low Power Drivers

SLIDE 5

Dynamic Power Consumption
Static Power Consumption
Process T

echnology

Architectural decisions

How to achieve this?

SLIDE 6

Switching & short circuit power
Pdyn = aC

tot VDD 2 F

– C

tot = C load + C par

– VDD - Supply Voltage – F – clock Frequency

Dynamic Power Consumption

Ctot VDD In Out discharge Charge

SLIDE 7

Voltage Scaling – Reducing the Supply Voltage

VDD VDD Logic High Logic Low

Limited by the ability to accurately differentiate between a 1 and 0

SLIDE 8

Remove unnecessary switching activity
Only clock necessary blocks
Remove clock from other blocks

Clock Gating

SLIDE 9

Clock frequency adjusted to meet requirements
Frequency islands

Frequency scaling

20M Hz 1M Hz 5M Hz Island Thresholds Island Thresholds Island Thresholds

SLIDE 10

Synchronous
Clock Driven
Pdyn  activity independent
Asynchronous
Event Driven
Pdyn  activity dependent

Asynchronous logic

SLIDE 11

The power a circuit consumes when it’s doing nothing!
Finite off Resistance
P = k VDD

– Voltage scaling – T

echnology

– Device Selection

High Vt Devices

Static – Leakage Power Reduction

Ctot In  1 Out  Roff VDD

SLIDE 12

Remove the power to inactive blocks
Leakage Power  zero

Power Gating

CM OS Block

VDD

SLIDE 13

Turning on and off sub-blocks to mininise the power consumption

Power Duty Cycling

T

slee p

Tturn-

T

Tturn-off Pon Pleakag

SLIDE 14

t sleep – time the device spends in sleep mode
Tturn-on – time the device/ block takes to turn on
T
n – active time
Tturn-off – time it takes to turn the device/ block off
Objective

– Pavg = 2x Pleakage

e.g. Pon = 100X Pleakage
T

sleep = 100 X T

Power Duty Cycling

Limited by the Leakage Current

SLIDE 15

Linear Region
Near Threshold
Sub Threshold

M OS Transistor Regions of operation

Linear Subthreshold Near Threshol d Source: www.design-reuse.com/news_img/20090316b_5.gif

SLIDE 16

T echnology Scaling – M oore – M ore than M oore

SLIDE 17

Technology Scaling – M oore – M ore than M oore

SLIDE 18

Technology Scaling – M oore – M ore than M oore

SLIDE 19

Process scaling will continue
Cost/ transistor no longer reducing
Energy density increasing
Leakage currents increasing
M ature process nodes here to stay

– Driven by reliability requirements – Cost

CM OS T echnology Scaling

Source: Z. Abbas, M. Oliveri “Impact of technology scaling

n leakage power in nano-scale bulk CMOS digital standard

cells” Microelectronics Journal

SLIDE 20

Full precision is not always required!
Circuits / Systems are over designed
Driven by QoS

Adequate computing

SLIDE 21

Source: EU Workshop ““Energy-Efficient Computing Systems, dynamic adaptation of Quality of Service and approximate computing”

SLIDE 22

Some recent developments

SLIDE 23

Conclusions

Significant progress in ULP design
Energy Gap is reducing
Most Power efficient block does not imply power

efficient system

Portfolio of tricks/techniques available
No silver bullet technique

SLIDE 24

M ethodologies for Reducing ULP Device Power Consumption

M icroelectronic Circuis Centre Ireland (M CCI), Tyndall Wednesday 30th M ay 2018

Energy Harvesting

consumption – architecting the design in a fashion which includes low power techniques – adopting a process which can reduce the consumption

these – one has to reach a compromise between power, performance, and cost

M otivation

– M obile revolution has really driven need for low power design

– Cost of removing the unused energy  Heat – Reliability

– Deploy and forget devices – Cost of transmitting data  move processing being done at the edge

Ultra Low Power Drivers

echnology

How to achieve this?

– C

– VDD - Supply Voltage – F – clock Frequency

Dynamic Power Consumption

Voltage Scaling – Reducing the Supply Voltage

VDD VDD Logic High Logic Low

Limited by the ability to accurately differentiate between a 1 and 0

Clock Gating

Frequency scaling

Asynchronous logic

– Voltage scaling – T

echnology

– Device Selection

Static – Leakage Power Reduction

Power Gating

Power Duty Cycling

T

Tturn-

T

Tturn-off Pon Pleakag

– Pavg = 2x Pleakage

Power Duty Cycling

Limited by the Leakage Current

M OS Transistor Regions of operation

T echnology Scaling – M oore – M ore than M oore

Technology Scaling – M oore – M ore than M oore

Technology Scaling – M oore – M ore than M oore

– Driven by reliability requirements – Cost

CM OS T echnology Scaling

Adequate computing

Some recent developments

Conclusions

efficient system

Thanks a lot for your time and attention! Any questions and/ or comments?

Q & A