LogSim LogSim A Logic Simulation Language A Logic Simulation Language
Why LogSim? Why LogSim? • Current hardware description languages • Current hardware description languages (eg eg, VHDL, , VHDL, Verilog Verilog) are cumbersome and ) are cumbersome and ( slow. slow. • Light • Light- -weight language weight language • Easy to learn • Easy to learn • Has only one data type, very simple • Has only one data type, very simple scoping and declarations scoping and declarations
VHDL is too big and too messy! VHDL is too big and too messy! -- -- VHDL code for n VHDL code for n- -bit counter (ESD figure 2.6) bit counter (ESD figure 2.6) -- -- by by Weijun Weijun Zhang, 04/ 2001 Zhang, 04/ 2001 library ieee ieee ; ; library use ieee.std_logic_1164.all; use ieee.std_logic_1164.all; use use ieee.std_logic_unsigned.all ieee.std_logic_unsigned.all; ; entity counter is entity counter is generic(n: natural := 2); : natural := 2); generic(n port( clock: in std_logic std_logic; clear: in ; clear: in std_logic std_logic; count: in ; count: in std_logic std_logic; Q: out ; Q: out port( clock: in std_logic_vector(n- -1 1 downto downto 0) ); 0) ); std_logic_vector(n end counter; end counter; architecture behv behv of counter is signal of counter is signal Pre_Q Pre_Q: std_logic_vector(n : std_logic_vector(n- -1 1 downto downto 0); 0); architecture begin begin -- behavior describe the counter behavior describe the counter -- process(clock, count, clear) begin , count, clear) begin process(clock if clear = '1' then if clear = '1' then Pre_Q Pre_Q < = < = Pre_Q Pre_Q - - Pre_Q Pre_Q; ; elsif (clock= '1' and elsif (clock= '1' and clock'event clock'event) then ) then if count = '1' then Pre_Q Pre_Q < = < = Pre_Q Pre_Q + 1; + 1; if count = '1' then end if; end if; end if; end if; end process; end process; -- concurrent assignment statement concurrent assignment statement -- Q < = Pre_Q Pre_Q; end ; end behv behv; ; Q < =
LogSim is simpler! LogSim is simpler! Component counter ( Component counter ( I n:not_used I n:not_used; ; Out:A,B,C,D Out:A,B,C,D){ ){ D:= !D; D:= !D; C:= !C * D + C* !D ; C:= !C * D + C* !D ; B:= !B * C * D + B * !(C* D); B:= !B * C * D + B * !(C* D); A:= !A * B * C * D + A * !(B* C* D); A:= !A * B * C * D + A * !(B* C* D); } } System(){ System(){ counter(0;A,B,C,D); counter(0;A,B,C,D); } }
LogSim Syntax LogSim Syntax • Component • Component- -oriented language, every oriented language, every component takes in inputs and returns component takes in inputs and returns outputs outputs • Every program is simply a series of • Every program is simply a series of components interconnected, all called components interconnected, all called from the System() component from the System() component
Data Type - - I I Data Type • Only one data type • Only one data type • Everything is just a signal. Signal is a • Everything is just a signal. Signal is a vector of bits. vector of bits. • For example, A= 101010; • For example, A= 101010; • Signal variables can be manipulated using • Signal variables can be manipulated using boolean operations, such as A + B * C operations, such as A + B * C boolean
Data Type - - II II Data Type • Individual bits of a signal can be indexed like in • Individual bits of a signal can be indexed like in an array. For example: A= 1010; A[0] = 1; an array. For example: A= 1010; A[0] = 1; //A is now 1011. //A is now 1011. • Vector • Vector- -slicing is also possible: slicing is also possible: A[1..3]= 101 A[1..3]= 101 • A signal can be truncated or extended: • A signal can be truncated or extended: A= 00001111; B$4= A; //B is now 1111 A= 00001111; B$4= A; //B is now 1111 A= 1111; B$8= A; //B is now 00001111 A= 1111; B$8= A; //B is now 00001111
Components Components • Basic building blocks of LogSim • Basic building blocks of LogSim • Every component takes in input signals and • Every component takes in input signals and saves results to output signals: saves results to output signals: Component myComponent(In myComponent(In: var1,var2; Out: var1, var2); : var1,var2; Out: var1, var2); Component • Components can be called from within the • Components can be called from within the System() component, or from other components System() component, or from other components • Calling a component is easy: • Calling a component is easy: System () { System () { myComponent(101,110; out1,out2); myComponent(101,110; out1,out2); } }
Operators Operators • () [] Component Instantiation, vector • () [] Component Instantiation, vector indexing indexing • …, $ Vector slicing, bit truncation/extension • …, $ Vector slicing, bit truncation/extension • * AND • * AND • # , + XOR, OR • # , + XOR, OR • := , = Sequential Assignment, • := , = Sequential Assignment, Combinational Assignment Combinational Assignment
The Compiler The Compiler
Parser and Lexer Lexer Parser and • ANTLR is used to write our compiler and • ANTLR is used to write our compiler and interpreter interpreter • Lexer • Lexer scans the source code, and outputs scans the source code, and outputs a stream of tokens. a stream of tokens. • Parser takes the tokens and builds an • Parser takes the tokens and builds an Abstract Syntax Tree (AST) using LR(1) Abstract Syntax Tree (AST) using LR(1) parser. parser.
Tree Walker Tree Walker • Walker builds the graph of the network • Walker builds the graph of the network using OperatorCollection using OperatorCollection • OperatorCollection OperatorCollection figures out the figures out the • dependencies as operators are added to it dependencies as operators are added to it • For components, the AST is stored in the • For components, the AST is stored in the symbol table and only when the symbol table and only when the component is instantiated, its AST is component is instantiated, its AST is walked walked
Topological Sort Topological Sort • Walker builds an acyclic graph of the • Walker builds an acyclic graph of the network with the data dependencies network with the data dependencies forming the edges of the graph forming the edges of the graph • But where do we start? • But where do we start? • Topological sort gives a schedule in which • Topological sort gives a schedule in which nodes can be evaluated nodes can be evaluated • Once sort is done, nodes are evaluated for • Once sort is done, nodes are evaluated for as many ticks as required as many ticks as required
Testing - - I I Testing • Small testing programs are written to test • Small testing programs are written to test individual features of LogSim (eg eg: : individual features of LogSim ( identifier, component, assignment, identifier, component, assignment, component instantiation) component instantiation) • More complex programs were written to • More complex programs were written to test the overall functionality of LogSim. test the overall functionality of LogSim. (eg eg, a 4 , a 4- -bit cyclic counter, a 4 bit cyclic counter, a 4- -bit ALU) bit ALU) (
Testing - - II II Testing • A shell script is written to automate the testing • A shell script is written to automate the testing of multiple programs. of multiple programs. • Initially, all test programs are run manually • Initially, all test programs are run manually once, with outputs saved to individual text files. once, with outputs saved to individual text files. • The script runs all test programs, and saves • The script runs all test programs, and saves outputs to a new set of text files. It then uses outputs to a new set of text files. It then uses “diff” to compare each original output file to the “diff” to compare each original output file to the newly saved output file. newly saved output file.
Lessons Learned Lessons Learned • Start early, even though we all kept our pace, • Start early, even though we all kept our pace, we were still slightly behind schedule towards we were still slightly behind schedule towards the end. the end. • Plan ahead, don’t immediately start coding • Plan ahead, don’t immediately start coding without knowing exactly what you want. We had without knowing exactly what you want. We had to back- -track several times due to unforeseeable track several times due to unforeseeable to back problems. problems. • Meet with Prof Edwards or your TA! Prof. • Meet with Prof Edwards or your TA! Prof. Edwards gave us hints/tips/insights on our Edwards gave us hints/tips/insights on our project that really speeded our progress project that really speeded our progress
Authors Authors • Nithya • Nithya Ganesan Ganesan Front- -end and back end and back- -end end Front • Mukul Khajanchi • Mukul Khajanchi Front- Front -end and backend end and backend • David Lau • David Lau Testing and Documentation Testing and Documentation • Joe Zhang • Joe Zhang Testing and Documentation Testing and Documentation
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