Logical Design 1 Zvi Kohavi and Niraj K. Jha Design with Basic - PDF document

Logical Design 1 Zvi Kohavi and Niraj K. Jha Design with Basic Logic Gates Logic gates: perform logical operations on input signals Positive (negative) logic polarity: constant 1 (0) denotes a high voltage and constant 0 a low (high) voltage Synchronous circuits: driven by a clock that produces a train of equally spaced pulses Asynchronous circuits: are almost free-running and do not depend on a clock; controlled by initiation and completion signals Fanout: number of gate inputs driven by the output of a single gate Fanin: bound on the number of inputs a gate can have Propagation delay: time to propagate a signal through a gate 2 1

Analysis of Combinational Circuits Circuit analysis: determine the Boolean function that describes the circuit • Done by tracing the output of each gate, starting from circuit inputs and continuing towards each circuit output Example: a multi-level realization of a full binary adder C 0 = AB + ( A + B ) C = AB + AC + BC S = ( A + B + C )[ AB + ( A + B)C ] ’ + ABC = ( A + B + C )( A’ + B’ )( A’ + C’ )( B’ + C’ ) + ABC = AB’C’ + A’BC’ + A’B’C + ABC = A B C 3 Simple Design Problems Parallel parity-bit generator: produces output value 1 if and only if an odd number of its inputs have value 1 z y x xy z 00 01 11 10 0 0 1 0 1 P 1 1 0 1 0 ( a ) Map. ( b ) Implementation. P = x’y’z + x’yz’ + xy’z’ + xyz 4 2

Simple Design Problems (Contd.) Serial-to-parallel converter: distributes a sequence of binary digits on a serial input to a set of different outputs, as specified by external control signals C 2 C 1 L 1 L 2 L 3 L 4 x 5 Logic Design with Integrated Circuits Small scale integration (SSI): integrated circuit packages containing a few gates; e.g., AND, OR, NOT, NAND, NOR, XOR Medium scale integration (MSI): packages containing up to about 100 gates; e.g., code converters, adders Large scale integration (LSI): packages containing thousands of gates; arithmetic unit Very large scale integration (VLSI): packages with millions of gates 6 3

Comparators n -bit comparator: compares the magnitude of two numbers X and Y , and has three outputs f 1 , f 2 , and f 3 • f 1 = 1 iff X > Y • f 2 = 1 iff X = Y • f 3 = 1 iff X < Y x 1 x 2 f 1 = x 1 x 2 y 2 ’ + x 2 y 1 ’y 2 ’ + x 1 y 1 ’ y 1 y 2 00 01 11 10 x 1 x 2 y 1 y 2 = ( x 1 + y 1 ’ ) x 2 y 2 ’ + x 1 y 1 ’ 00 2 1 1 1 f 2 = x 1 ’x 2 ’y 1 ’y 2 ’ + x 1 ’x 2 y 1 ’y 2 + 01 3 2 1 1 2-bit comparator x 1 x 2 ’y 1 y 2 ’ + x 1 x 2 y 1 y 2 11 3 3 2 3 = x 1 ’y 1 ’ ( x 2 ’y 2 ’ + x 2 y 2 ) + f 1 f 2 f 3 3 10 3 1 2 x 1 y 1 ( x 2 ’y 2 ’ + x 2 y 2 ) = ( x 1 ’y 1 ’ + x 1 y 1 )( x 2 ’y 2 ’ + x 2 y 2 ) ( a ) Block diagram. ( b ) Map for f 1 , f 2 , and f 3 . f 3 = x 2 ’y 1 y 2 + x 1 ’x 2 ’y 2 + x 1 ’y 1 x 1 = x 2 ’y 2 ( y 1 + x 1 ’ ) + x 1 ’y 1 y 1 f 1 x 2 y 2 x 1 y 1 7 ( c ) Circuit for f 1 . 4-bit/12-bit Comparators Four-bit comparator: 11 inputs (four for X , four for Y , and three connected to outputs f 1 , f 2 and f 3 of the preceding stage) 12-bit comparator: x 1 x 4 y 1 y 4 f 1 > > Inputs from f 2 = = preceding stage f 3 < < ( a ) A 4-bit comparator. x 1 x 4 y 1 y 4 x 5 x 8 y 5 y 8 x 9 x 12 y 9 y 12 f 1 0 > > > > > > f 2 = = = = = = 1 f 3 < < < < < < 0 ( b ) A 12-bit comparator. 8 4

Data Selectors Multiplexer: electronic switch that connects one of n inputs to the output Data selector: application of multiplexer • n data input lines, D 0 , D 1 , …, D n -1 • m select digit inputs s 0 , s 1 , …, s m- 1 • 1 output 9 Implementing Switching Functions with Data Selectors Data selectors: can implement arbitrary switching functions Example: implementing two-variable functions 10 5

Implementing Switching Functions with Data Selectors (Contd.) To implement an n -variable function: a data selector with n -1 select inputs and 2 n -1 data inputs Implementing three-variable functions: z = s 2 ’s 1 ’D 0 + s 2 ’s 1 D 1 + s 2 s 1 ’D 2 + s 2 s 1 D 3 Example: s 1 = A , s 2 = B , D 0 = C , D 1 = 1, D 2 = 0, D 3 = C’ z = A’B’C + AB’ + ABC’ = AC’ + B’C General case: Assign n -1 variables to the select inputs and last variable and constants 0 and 1 to the data inputs such that desired function results 11 Priority Encoders Priority encoder: n input lines and log 2 n output lines • Input lines represent units that may request service • When inputs p i and p j , such that i > j , request service simultaneously, line p i has priority over line p j • Encoder produces a binary output code indicating which of the input lines requesting service has the highest priority Example: Eight-input, three-output priority encoder Enable Input lines Outputs p 0 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 z 4 z 2 z 1 p 1 1 0 0 0 0 0 0 0 0 0 0 p 2 z 1 1 0 0 0 0 0 0 0 0 1 p 3 Priority 1 0 0 0 0 0 0 1 0 z 2 p 4 encoder 1 0 0 0 0 0 1 1 p 5 z 4 1 0 0 0 1 0 0 p 6 0 0 1 0 1 1 p 7 1 0 1 1 0 1 1 1 1 z 0 ( a ) Block diagram. ( b ) Truth table . z 4 = p 4 p 5 ’p 6 ’p 7 ’ + p 5 p 6 ’p 7 ’ + p 6 p 7 ’ + p 7 = p 4 + p 5 + p 6 + p 7 z 2 = p 2 p 3 ’p 4 ’p 5 ’p 6 ’p 7 ’ + p 3 p 4 ’p 5 ’p 6 ’p 7 ’ + p 6 p 7 ’ + p 7 = p 2 p 4 ’p 5 ’ + p 3 p 4 ’p 5 ’ + p 6 + p 7 12 z 1 = p 1 p 2 ’p 3 ’p 4 ’p 5 ’p 6 ’p 7 ’ + p 3 p 4 ’p 5 ’p 6 ’p 7 ’ + p 5 p 6 ’p 7 ’ + p 7 = p 1 p 2 ’p 4 ’p 6 ’ + p 3 p 4 ’p 6 ’ + p 5 p 6 ’ + p 7 6

Priority Encoders (Contd.) p 0 p 1 p 2 z 1 p 3 p 4 p 5 z 2 p 6 z 4 p 7 Request indicator Enable z 0 ( c ) Logic diagram. 13 Decoders Decoders with n inputs and 2 n outputs: for any input combination, only one output is 1 Useful for: • Routing input data to a specified output line, e.g., in addressing memory • Basic building blocks for implementing arbitrary switching functions • Code conversion • Data distribution Example: 2-to-4- decoder w x f 0 = w x f 1 = w x f 2 = wx 14 f 3 = wx 7

Decoders (Contd.) Example: 4-to-16 decoder made of two 2-to-4 decoders and a gate- switching matrix 15 Decimal Decoder BCD-to-decimal: 4-to-16 decoder made of two 2-to-4 decoders and a gate- switching matrix w x y z f 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 Enable 16 ( c ) Logic diagram. 8

Decimal Decoder (Contd.) Implementation using a partial-gate matrix: 17 Implementing Arbitrary Switching Functions Example: Realize a distinct minterm at each output 18 9

Demultiplexers Demultiplexers: decoder with1 data input and n address inputs • Directs input to any one of the 2 n outputs C 2 C 1 Example: A 4-output demultiplexer L 1 L 2 L 3 19 L 4 x Seven-segment Display Seven-segment display: BCD to seven-segment decoder and seven LEDs Seven-segment pattern and code: A = x 1 + x 2 ’x 4 ’ + x 2 x 4 + x 3 x 4 B = x 2 ’ + x 3 ’x 4 ’ + x 3 x 4 C = x 2 + x 3 ’ + x 4 D = x 2 ’x 4 ’ + x 2 ’x 3 + x 3 x 4 ’ + x 2 x 3 ’x 4 E = x 2 ’x 4 ’ + x 3 x 4 ’ F = x 1 + x 2 x 3 ’ + x 2 x 4 ’ + x 3 ’x 4 ’ G = x 1 + x 2 ’ x 3 + x 2 x 3 ’ + x 3 x 4 ’ 20 10

Sine Generators Combinational sine generators: for fast and repeated evaluation of sine • Input: angle in radians converted to binary • Output: sine in binary Angle x sin( x ) x 1 x 2 x 3 x 4 z 1 z 2 z 3 z 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 z 1 = x 1 ’ x 2 + x 1 x 2 ’ + x 2 x 3 ’ + x 1 ’x 3 x 4 1 0 1 0 0 0 0 1 z 2 = x 1 x 2 ’ + x 3 x 4 ’ + x 1 ’x 2 x 4 0 0 1 1 1 0 0 0 1 0 0 0 1 0 1 1 z 3 = x 3 x 4 ’ + x 2 x 3 + x 2 x 4 ’ + 0 1 0 1 1 1 0 1 x 2 ’ x 3 ’x 4 + x 1 x 4 ’ 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 z 4 = x 2 ’x 3 ’x 4 + x 2 x 3 ’ x 4 ’ + x 1 x 2 ’x 3 ’ + 1 0 0 0 1 1 1 1 x 1 x 3 x 4 + x 1 ’x 2 x 4 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 21 ( a ) Truth table . NAND/NOR Circuits Switching algebra: not directly applicable to NAND/NOR logic NAND and NOR gate symbols 22 11

Analysis of NAND/NOR Networks Example: circles (inversions) at both ends of a line cancel each other A 5 T = A + ( B + C )( D + EF ) B B + C 3 C 4 [( B + C )( D + EF )] D 2 D + EF E 1 F ( EF ) ( a ) NAND-logic circuit. A T = A + ( B + C )( D + EF ) B B + C C ( B + C )( D + EF ) D D + EF E F EF ( b ) Logically equivalent AND-OR circuit. 23 Synthesis of NAND/NOR Networks Example: Realize T = w ( y+z ) + xy’z’ [ w ( y + z )] w y 2 1 z y + z 4 T = w ( y + z ) + xy z x y 3 z ( xy z ) ( a ) First realization. [ w ( y + z )] w y y + z 2 1 z 4 T = w ( y + z ) + xy z x y 3 3 z ( y z ) y z ( xy z ) ( b ) Realization with two-input gates. 24 12

Design of High-speed Adders Full adder: performs binary addition of three binary digits • Inputs: arguments A and B and carry-in C • Outputs: sum S and carry-out C 0 Example: Truth table, block diagram and expressions: S = A’B’C + A’BC’ + AB’C’ + ABC = A B C C 0 = A’BC + ABC’ + AB’C + ABC = AB + AC + BC 25 Ripple-carry Adder Ripple-carry adder: Stages of full adders • C f : forced carry • C 0 ( n-1 ) : overflow carry S i = A i B i C i C 0i = A i B i + A i C i + B i C i Time required: • Time per full adder: 2 units • Time for ripple-carry adder: 2 n units 26 13