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Living with Uncertainty
Jim Dodrill ARM
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We want our variation models to be:
Living with Uncertainty Jim Dodrill ARM 1 We want our variation - - PowerPoint PPT Presentation
Living with Uncertainty Jim Dodrill ARM 1 We want our variation - - PowerPoint PPT Presentation
Living with Uncertainty Jim Dodrill ARM 1 We want our variation models to be: Effective Efficient Accurate Enough 2 Stage-Based OCV The dependence of the derate on input transition time and output load is not captured This will
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Stage-Based OCV
§ The dependence of the derate on input transition time and
- utput load is not captured
§ This will be addressed by adopting LVF as soon as it is practical
slew sigma load
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Voltage Variation
§ Voltage variation accounts for about half of the derate
§ Even more for lower voltages and/or higher VT logic
1% 51% 48% temperature variation voltage variation process variation
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Gaussian Voltage Variation
§ Most variation characterization is done with a full Gaussian
voltage distribution
VDD VDD-10% VDD+10% 3σ
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Example IR Drop Allocations
bump power regulator
Global distribution Mtop to M6 M6 M5 M4 M3 M2 M2+M1 package route
ball
board trace
1 2 3 4 5 6 cell bump
Global distribution Mtop to M6 M6 M5 M4 M3 strap package route
ball
board trace
10 9 8 7
GND
M2+M1
power gate
7% 3%
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domain VDD VDD-10% VDD+10% VDD-5% VDD+5% Fast Slow 3σ 3σ
Rectified Voltage Distribution
§ A more realistic voltage distribution
§ Needs support from EDA vendors
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Setup and Hold Margins
§ Setup and hold times are not really hard boundaries
§ Statistical constraint characterization is an expensive way
to precisely quantify an imprecise value
§ Need a more efficient and flexible specification
Propagation delay Data arrival w.r.t. clock
tsu_tp_r th_tp_r
Setup and hold are defined by a specified increase in CK->Q
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Standard Deviations
§ The number of standard deviations from the mean is Nσ
§ It is often set to 3σ § It is hard coded into SBOCV tables and statistical hold margins § Sigma based OCV frees users to set Nσ for their design
§ But what is the real yield impact of choosing Nσ?
§ A design with many critical hold paths may want more than 3σ § Trying to close timing with conservative margins may hurt overall PPA § What fraction of total yield failures are due to timing marginality?
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Aging
§ Today’s critical path is not tomorrow’s critical path § Aging is:
§ A stochastic process § not deterministic § Workload dependent § Switching activity § Power gating profile
§ It is not correct to
simply re-time with aged models
§ Need EDA support
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Cost
§ The cost to IP providers of creating variation models can be
an order of magnitude higher than the cost of providing timing models
§ Need innovative approaches to modeling variation efficiently
§ Expect a trade-off between accuracy and cost
§ Ask about how your IP provider determined the trade-off they applied
§ Expect a push toward more standardization of
§ PVT corners § Voltage variation distributions § Temperature variation distributions § Standard deviations
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END
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Bio
Jim Dodrill received his education at Oklahoma State University and Duke University. During is career he has done custom circuit design and layout, synthesis and place-and-route, full chip assembly, physical and timing verification, internal CAD software development and management. He is currently a Senior Principal Design Engineer in the Advanced Products Division of the Physical Design Group at ARM in Austin, Texas. There he is developing new physical IP and modeling methodology. His current emphasis is on modeling
- n-chip variation.