Lecture 9: Sequential Networks: Implementation CSE 140: Components - - PowerPoint PPT Presentation

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Lecture 9: Sequential Networks: Implementation CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 Implementation

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Lecture 9: Sequential Networks: Implementation

CSE 140: Components and Design Techniques for Digital Systems Spring 2014

CK Cheng, Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

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Implementation

  • Format and Tool
  • Procedure
  • Excitation Tables
  • Example

2

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Mealy Machine: yi(t) = fi(X(t), S(t)) Moore Machine: yi(t) = fi(S(t)) si(t+1) = gi(X(t), S(t))

C1 C2

CLK x(t) y(t)

Mealy Machine C1 C2

CLK x(t) y(t)

Moore Machine

S(t) S(t)

Canonical Form: Mealy and Moore Machines

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Understanding Current State and Next State in a sequential circuit

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today sunrise

Preparing for tomorrow according to our effort today

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C1 C2

CLK x(t) y(t)

Implementation Format

Q(t)

Q(t+1) = h(x(t), Q(t)) Circuit C1 y(t) = f(x(t), Q(t)) Circuit C2

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Canonical Form: Mealy & Moore machines State Table à Netlist Tool: Excitation Table

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Implementation Tool: Excitation Table

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x(t) Q(t)

CLK

C1

id x(t) Q(t) Q(t+1) 1 1 1 1 2 1 3 1 1

State Table Find D, T, (S R), (J K) to drive F-Fs

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Implementation Tool: Excitation Table

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x(t) Q(t)

CLK

Q(t)

C1

id x(t) Q(t) T(t) Q(t+1) 1 1 1 1 1 1 2 1 1 3 1 1 1 id x(t) Q(t) Q(t+1) 1 1 1 1 2 1 1 3 1 1

State Table Excitation Table Example with T flip flop

T(t)

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Implementation Tool: Excitation Table

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x(t) Q(t)

CLK

Q(t)

C1

id x(t) Q(t) T(t) Q(t+1) 1 1 1 1 1 1 2 1 1 3 1 1 1

Excitation Table

Implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t))

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Implementation: Procedure

State Table => Excitation Table

Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)).

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Implementation: Procedure

State Table => Excitation Table

Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)).

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Implementation: Procedure

F-F State Table <=> F-F Excitation Table

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DTSRJK PS Q(t) NS Q(t+1) NS Q(t+1) PS Q(t) DTSRJK

  • D F-F
  • D(t)= eD(Q(t+1), Q(t))
  • T F-F
  • T(t)= eT(Q(t+1), Q(t))
  • SR F-F
  • S(t)= eS(Q(t+1), Q(t))
  • R(t)= eR(Q(t+1), Q(t))
  • JK F-F
  • J(t)= eJ(Q(t+1), Q(t))
  • K(t)= eK(Q(t+1), Q(t))
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State table of JK F-F:

00 1 01 10 1 1 11 1 1 Q(t) Q(t+1) JK

Excitation table of JK F-F:

0-

  • 1

1 1-

1 PS NS Q(t) Q(t+1) JK

If Q(t) is 1, and Q(t+1) is 0, then JK needs to be -1.

Excitation Table

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Excitation Tables and State Tables

0- 01 1 10

1 PS NS Q(t) Q(t+1)

SR Excitation Tables:

1 1 1 1 PS NS Q(t) Q(t+1)

T

00 1 01 1 PS SR Q(t) Q(t+1)

SR

10 1 1 11

  • 1

1 1 1 PS T Q(t) Q(t+1)

T State Tables:

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0-

  • 1

1 1-

1 PS NS Q(t) Q(t+1)

JK Excitation Tables:

1 1 1 1 PS NS Q(t) Q(t+1)

D

00 1 01 1 PS JK Q(t) Q(t+1)

JK

10 1 1 11 1 1 1 1 1 PS D Q(t) Q(t+1)

D State Tables:

Excitation Tables and State Tables

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Implementation: Procedure

  • 1. State table: y(t)= f(Q(t), x(t)), Q(t+1)= h(x(t),Q(t))
  • 2. Excitation table of F-Fs:
  • D(t)= eD(Q(t+1), Q(t));
  • T(t)= eT(Q(t+1), Q(t));
  • (S, R), or (J, K)
  • 3. From 1 & 2, we derive excitation table of the system
  • D(t)= gD(x(t),Q(t))= eD(h(x(t),Q(t)),Q(t));
  • T(t)= gT(x(t),Q(t))= eT(h(x(t),Q(t)),Q(t));
  • (S, R) or (J, K).
  • 4. Use K-map to derive optional combinational logic

implementation.

  • D(t)= gD(x(t),Q(t))
  • T(t)= gT(x(t),Q(t))
  • y(t)= f(x(t),Q(t))

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Implementation: Example Implement a JK F-F with a T F-F

00 1 01 1 PS JK Q(t)

Q(t+1) = h(J(t),K(t),Q(t)) = J(t)Q’(t)+K’(t)Q(t) JK

10 1 1 11 1

Implement a JK F-F:

Q Q’ C1 J K T

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Q

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id 1 2 3 4 5 6 7 J(t) 1 1 1 1 K(t) 1 1 1 1 Q(t) 1 1 1 1 Q(t+1) 1 1 1 1 T(t) 1 1 1 1 1 1 1 1 PS NS Q(t) Q(t+1)

Excitation Table of T Flip-Flop T(t) = Q(t) ⊕ Q(t+1) T(t) = Q(t) XOR ( J(t)Q’(t) + K’(t)Q(t)) Excitation Table of the Design

Example: Implement a JK flip-flop using a T flip-flop

T

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0 2 6 4 1 3 7 5

Q(t)

J

0 0 1 1 0 1 1 0

K

T(J,K,Q): T = K(t)Q(t) + J(t)Q’(t)

Q Q’ J K T

Example: Implement a JK flip-flop using a T flip-flop

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iClicker

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Given a flip-flop, the relation of its state table and excitation table is

  • A. One to one
  • B. One to many
  • C. Many to one
  • D. Many to many
  • E. None of the above
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Let’s implement our free running 2-bit counter using T-flip flops

S0 S1 S2 S3

PS

Next state

S1 S2 S3 S0 State Table

S0 S1 S2 S3

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Let’s implement our free running 2-bit counter using T-flip flops

S0 S1 S2 S3

S1 S2 S3 S0 State Table

S0 S1 S2 S3

State Table with Assigned Encoding

0 0 0 1 1 0 1 1

Current

01 10 11 00

Next

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 2 1 1 1 3 1 1

Excitation table

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Excitation table

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Excitation table

T0(t) = T1(t) = Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t)

Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Excitation table

T0(t) = 1 T1(t) = Q0(t)

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T Q Q’ T Q Q’

Q0 Q1 1 T1

Free running counter with T flip flops

T0(t) = 1 T1(t) = Q0(t)

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

Assign mapping a:0, b:1

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

Assign mapping a:0, b:1 PI Q How many states should the pattern recognizer have A. One because it has one output B. One because it has one input C. Two because the input can be one of two states (a or b) D. Three because . .. . . . . E. Four because . . . . .

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PI Q: How many states should the pattern recognizer have A. One because it has one output B. One because it has one input C. Two because the input can be one of two states (a or b) D. Three because . .. . . . . E. Four because . . . . .

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

S1 S0

a/0 b/0 a/0 b/1

S2

a/0 b/0

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State Diagram => State Table with State Assignment

State Assignment S0: 00 S1: 01 S2: 10

PS\x a b S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1 PS\x 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1 Q1(t+1)Q0(t+1), y a: 0 b: 1

S1 S0

a/0 b/0 a/0 b/1

S2

a/0 b/0

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Example 2: State Diagram => State Table => Excitation Table => Netlist PS\x 0 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1

id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 00 4 100 10 5 101 00 1 6 110

  • 7

111

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0 2 6 4 1 3 7 5

x(t) Q1

0 1 - 1 0 0 - 0

Q0

D1(t): D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 00 4 100 10 5 101 00 1 6 110

  • 7

111

  • Example 2: State Diagram => State Table

=> Excitation Table => Netlist

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D Q Q’ D Q Q’ Q1 Q0 D1 D0

Q0

Q1 x’

D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x x y Q’1 Q’0 x’ Example 2: State Diagram => State Table => Excitation Table => Netlist

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D Q Q’ D Q Q’ Q1 Q0 D1 D0

Q0

Q1 x’

x y Q’1 Q’0 x’

Example 3: State Diagram => State Table => Excitation Table => Netlist S1 S0

a/0 b/0 a/0 b/1

S2

a/0 b/0

iClicker: The relation between the above state diagram and sequential circuit.

  • A. One to one.
  • B. One to many
  • C. Many to one
  • D. Many to many

E. None of the above

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Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t)

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Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t) y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 1 1 0 1 1

PS

input

x=0 x=1

Q1(t) Q0(t) | (Q1(t+1) Q0(t+1), y(t)) Present State | Next State, Output

S0 S1 S2 S3

PS

input

x=0 x=1

Netlist ó State Table ó State Diagram ó Input Output Relation

State Assignment

Characteristic Expression:

y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 1 1 0 1 1

PS

input

x=0 x=1 01, 0 00, 0 10, 0 00, 0 11, 0 00, 0 00, 1 00, 1

Q1(t) Q0(t) | Q1(t+1) Q0(t+1), y(t) Present State | Next State, Output

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1

Let: S0 = 00 S1 = 01 S2 = 10 S3 = 11

Remake the state table using symbols instead of binary code , e.g. ’00’ Netlist ó State Table ó State Diagram ó Input Output Relation

State Assignment

y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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Netlist ó State Table ó State Diagram ó Input Output Relation Given inputs and initial state, derive output sequence

S1 S2 S3 S0

Time 1 2 3 4 5 Input 1

  • State

S0 Output

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1

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Netlist ó State Table ó State Diagram ó Input Output Relation Example: Given inputs and initial state, derive

  • utput sequence

Time 1 2 3 4 5 Input 1

  • State

S0 S1 S0 S1 S2 S3 Output 0 1

(0 or 1)/1

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1

x/y

S1 S2 S3 S0

0/0 0/0 0/0 1/0 1/0 1/0

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Finite State Machine Example

  • Traffic light controller

– Traffic sensors: TA, TB (TRUE when there’s traffic) – Lights: LA, LB

TA LA TA LB TB TB LA LB

Academic Ave. Bravado Blvd. Dorms Fields Dining Hall Labs

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FSM Black Box

  • Inputs: CLK, Reset, TA, TB
  • Outputs: LA, LB

TA TB LA LB CLK Reset Traffic Light Controller

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FSM State Transition Diagram

  • Moore FSM: outputs labeled in each state
  • States: Circles
  • Transitions: Arcs

S0 LA: green LB: red Reset

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FSM State Transition Diagram

  • Moore FSM: outputs labeled in each state
  • States: Circles
  • Transitions: Arcs

S0 LA: green LB: red S1 LA: yellow LB: red S3 LA: red LB: yellow S2 LA: red LB: green TA TA TB TB Reset

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FSM State Transition Table

PS Inputs NS TA TB S0 X S1 S0 1 X S0 S1 X X S2 S2 X S3 S2 X 1 S2 S3 X X S0

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State Transition Table

PS Inputs NS Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1) X 1 1 X 1 X X 1 1 X 1 1 1 X 1 1 1 1 X X

State Encoding S0 00 S1 01 S2 10 S3 11

Q1(t+1)= Q1(t)xor Q0(t) Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B

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FSM Output Table

PS Outputs Q1 Q0 LA1 LA0 LB1 LB0 1 1 1 1 1 1 1 1 1 1

Output Encoding green 00 yellow 01 red 10

LA1 = Q1 LA0 = Q’1Q0 LB1 = Q’1 LB0 = Q1Q0

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FSM Schematic: State Register

S1 S0 S'1 S'0 CLK

state register

Reset r

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Logic Diagram

S1 S0 S'1 S'0 CLK

next state logic state register

Reset TA TB

inputs

S1 S0 r

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FSM Schematic: Output Logic

S1 S0 S'1 S'0 CLK

next state logic

  • utput logic

state register

Reset LA1 LB1 LB0 LA0 TA TB

inputs

  • utputs

S1 S0 r

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Summary: Implementation

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  • Set up canonical form
  • Mealy or Moore machine
  • Identify the next states
  • state diagram ⇨ ¡state table
  • state assignment
  • Derive excitation table
  • Inputs of flip flops
  • Design the combinational logic
  • don’t care set utilization