Lecture 9: Finite State Machines And Sequential Circuit Design - PowerPoint PPT Presentation

Lecture 9: Finite State Machines And Sequential Circuit Design (contd) CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering 1 University of California, San Diego

Moore FSM for the Mars Life Recognizer Which of the following diagrams is a correct Moore solution to the ‘001’ pattern recognizer? 1/1 1/0 A. 0/0 0/0 S0 S1 S2 0/0 1/0 B. 1 0 1 1 0 0 S0 S1 S2 S3 0 0 0 1 1 0 C. Both A and B are correct 2 D. None of the above

Alternate representation of FSM Diagrams 1 0 1 1 0 0 S2 S3 S0 S1 0 1 0 0 1 0 S2 S3 S0 S1 0 1 0 0 3

Moore Mars Life Recognizer: FF Input Specs Pattern Recognizer ‘001’ x(t) y(t) C1 C2 1 0 1 1 0 0 S0 S1 S2 S3 CLK 0 0 0 1 S(t) 1 0 Moore Machine What does state table need to show to design controls of C2? A. (current input x(t), current state S(t) vs. next state, S(t+1)) B. (current input, current state vs. current output y(t)) C. (current state vs. current output y(t) and next state) D. (current state vs. current output y(t) ) E. None of the above 4

Moore Mars Life Recognizer: State Table 1 0 1 1 0 0 S0 S1 S2 S3 0 0 0 1 1 0 ID Q 1 Q 0 x D 1 D 0 y S(t)\x 0 1 000 0 0 1 0 S0 S1,0 S0,0 001 1 0 0 0 S1 S2,0 S0,0 S2 S2,0 S3,0 010 2 1 0 0 S3 S1,1 S0,1 011 3 0 0 0 Q 1 Q 0 \x 0 1 100 4 1 0 0 00 01,0 00,0 101 5 1 1 0 01 10,0 00,0 110 6 0 1 1 10 10,0 11,0 11 01,1 00,1 111 7 0 0 1 Q 1 (t+1)Q 0 (t+1), y

Mars Life Recognizer: Combinational Circuit Design Q 0 D 1 (t): 0 2 6 4 0 1 0 1 1 3 7 5 0 0 0 1 x(t) id Q 1 Q 0 x D 1 D 0 y Q 1 000 0 0 1 0 Q 0 D 0 (t): 001 1 0 0 0 0 2 6 4 1 0 1 0 010 2 1 0 0 1 3 7 5 0 0 0 1 011 3 0 0 0 x(t) 100 Q 1 4 1 0 0 Q 0 y(t): 101 5 1 1 0 0 2 6 4 0 0 1 0 110 6 0 1 1 1 3 7 5 0 0 1 0 111 7 0 0 1 x(t) Q 1

Mars Life Recognizer Circuit Implementation State Diagram => State Table => Excitation Table => Circuit Q 0 D 0 y Q D Q’ Q 1 D 1 Q D Q’ 0 1 1 D 1 (t)= Q 1 (t)Q 0 (t)’+Q 1 (t)’Q 0 (t) x(t) 1 D 0 (t)= Q 1 (t)’Q 0 (t)’x(t)’+ 0 0 S0 S1 S2 S3 0 0 0 1 Q 1 (t)Q 0 (t) x(t)’+Q 1 (t)Q 0 (t)’ x(t) y(t)= Q 1 (t)Q 0 (t) 1 0 7

FSM Specification x(t) Q D Q’ Q 0 (t) Q Q 0 (t) D Q’ Q 1 (t) y(t) Q 1 (t) CLK 8

From circuit to FSM x(t) Q D Q’ Q 0 (t) Q y(t) Q 0 (t) D Q’ Q 1 (t) Q 1 (t) CLK y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t)) 9

Netlist ó State Table ó State Diagram ó Input Output Relation Characteristic Expression: y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t)) State table input x=0 x=1 PS 0 0 0 1 1 0 1 1 Q 1 (t) Q 0 (t) | (Q 1 (t+1) Q 0 (t+1), y(t)) Present State | Next State, Output 10

Netlist ó State Table ó State Diagram ó Input Output Relation y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t)) State table State Assignment input input x=0 x=1 PS x=0 x=1 Let: PS S 0 = 00 S 1 , 0 S 0 , 0 S 0 0 0 01, 0 00, 0 S 1 = 01 S 2 , 0 S 0 , 0 S 1 0 1 10, 0 00, 0 S 2 = 10 S 3 , 0 S 0 , 0 S 2 1 0 11, 0 00, 0 S 3 = 11 S 0 , 1 S 0 , 1 S 3 1 1 00, 1 00, 1 Q 1 (t) Q 0 (t) | Q 1 (t+1) Q 0 (t+1), y(t) Remake the state table using symbols Present State | Next State, Output instead of binary code , e.g. ’00’ 11

Netlist ó State Table ó State Diagram ó Input Output Relation input x=0 x=1 PS S 2 S 3 S 0 S 1 S 1 , 0 S 0 , 0 S 0 S 2 , 0 S 0 , 0 S 1 S 3 , 0 S 0 , 0 S 2 S 0 , 1 S 0 , 1 S 3 12

Netlist ó State Table ó State Diagram ó Input Output Relation 1 input 1 x=0 x=1 1 PS S 2 S 3 S 0 S 1 S 0 S 1 , 0 S 0 , 0 0 0 0 0 1 0 0 S 1 S 2 , 0 S 0 , 0 S 2 S 3 , 0 S 0 , 0 (0 or 1) S 3 S 0 , 1 S 0 , 1 Example: Given inputs and initial state, derive output sequence Time 0 1 2 3 4 5 Input 0 1 0 0 0 - State S0 S1 S0 S1 S2 S3 Output 0 0 0 0 0 1 13

Finite State Machine Example • Traffic light controller – Traffic sensors: T A , T B (TRUE when there’s traffic) – Lights: L A , L B Bravado Dining Hall L B L A T B L A Academic Ave. T A T A Dorms L B T B Labs Blvd. Fields 14

FSM Black Box • Inputs: CLK , Reset , T A , T B • Outputs: L A , L B CLK Traffic T A L A Light T B L B Controller Reset 15

FSM State Transition Diagram • Moore FSM: outputs labeled in each state Bravado Dining • States: Circles Hall L B • Transitions: Arcs L A T B L A Reset Academic Ave. T A T A S0 Dorms L B T B Labs L A : green L B : red Blvd. Fields 16

FSM State Transition Diagram Bravado Dining Hall • Moore FSM: outputs labeled in each state L B L A T B L A Academic Ave. T A T A Dorms L B T B Labs Blvd. T A Fields Reset T A S0 S1 L A : green L A : yellow Which of the following is true about L B : red L B : red the controller? A. The traffic light on Academic Ave (L A ) remains green as long as there is traffic on that street B. The traffic light on both avenues are green for exactly once clock S3 S2 cycle in every four clock cycles L A : red L A : red L B : yellow L B : green T B T B 17

FSM State Transition Table T A PS Inputs NS Output Reset T A S0 S1 T A T B L A L B L A : green L A : yellow L B : red L B : red S0 0 X S1 S0 1 X S0 S1 X X S2 S2 X 0 S3 S3 S2 L A : red L A : red S2 X 1 S2 L B : yellow L B : green T B T B S3 X X S0 18

FSM State Transition Table PS Inputs NS Output T A Reset T A T A T B L A L B S0 S1 L A : green L A : yellow S0 0 X S1 green red L B : red L B : red S0 1 X S0 green red S1 X X S2 yellow red S2 X 0 S3 red green S3 S2 S2 X 1 S2 red green L A : red L A : red L B : yellow L B : green T B S3 X X S0 red yellow T B PS Inputs NS Q 1 (t) Q 0 (t) T A T B Q 1 (t +1) Q 0 (t +1) State Encoding 0 0 0 X 0 1 S0 00 0 0 1 X 0 0 S1 01 0 1 X X 1 0 1 0 X 0 1 1 S2 10 1 0 X 1 1 0 S3 11 1 1 X X 0 0 19

State Transition Table PS Inputs NS Q 1 (t) Q 0 (t) T A T B Q 1 (t +1) Q 0 (t +1) 0 0 0 X 0 1 0 0 1 X 0 0 0 1 X X 1 0 1 0 X 0 1 1 1 0 X 1 1 0 1 1 X X 0 0 Q 1 (t+1)= Q 1 (t) xor Q 0 (t) Q 0 (t+1)= Q’ 1 (t) Q’ 0 (t) T’ A + Q 1 (t) Q’ 0 (t) T’ B 20

Logic Diagram CLK S 1 =Q 1 S' 1 S 1 S 0 =Q 0 T A S' 0 S 0 r T B Reset S 1 S 0 inputs next state logic state register Q 1 (t+1)= Q 1 (t) xor Q 0 (t) Q 0 (t+1)= Q’ 1 (t) Q’ 0 (t) T’ A + Q 1 (t) Q’ 0 (t) T’ B 21

FSM Output Table T A PS Inputs NS Output Reset T A S0 S1 T A T B L A L B L A : green L A : yellow L B : red L B : red S0 0 X S1 green red S0 1 X S0 green red S1 X X S2 yellow red S2 X 0 S3 red green S3 S2 L A : red L A : red S2 X 1 S2 red green L B : yellow L B : green T B S3 X X S0 red yellow T B PS Outputs Output Encoding Q 1 Q 0 L A 1 L A 0 L B 1 L B 0 green 00 L A 1 = Q 1 0 0 0 0 1 0 L A 0 = Q’ 1 Q 0 0 1 0 1 1 0 yellow 01 L B 1 = Q’ 1 1 0 1 0 0 0 red 10 L B 0 = Q 1 Q 0 1 1 1 0 0 1 22

FSM Schematic: Output Logic CLK L A1 S' 1 S 1 L A0 T A S' 0 S 0 L B1 r T B Reset S 1 S 0 L B0 inputs next state logic state register output logic outputs L A 1 = Q 1 L A 0 = Q’ 1 Q 0 L B 1 = Q’ 1 L B 0 = Q 1 Q 0 23

Summary: Implementation • Set up canonical form • Mealy or Moore machine • Identify the next states • state diagram ⇨ ¡ state table • state assignment • Derive excitation table • Inputs of flip flops • Design the combinational logic • don’t care set utilization 24