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Lecture 3: Verification of Weak Memory Models Part 1: State Reachability Problem Ahmed Bouajjani LIAFA, University Paris Diderot Paris 7 [Atig, B., Burckhardt, Musuvathi, POPL10, ESOP12] [Atig, B., Parlato, 2011] VTSA, MPI-Saarbr

  1. Getting rid of Store Buffers [Atig, B., Parlato, 2011] When is it possible to reduce TSO verification to SC verification ? Find restrictions on the explored behaviors such that: Given a concurrent program P, it is possible to build a concurrent program P ′ such that: running P with TSO semantics under these restrictions is equivalent to running P ′ with SC semantics. A notion of Context-Bounded Analysis for TSO Unbounded number of context-switches: Bounding the age of each write in the buffer in terms of context-switches. ⇒ Transfer decidability/complexity results from SC to TSO. ⇒ Use existing tools for concurrent programs under SC. A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 12 / 42

  2. The rest of the lecture Decidability and complexity for TSO: Simulations by/of Lossy Channel Systems A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 13 / 42

  3. The rest of the lecture Decidability and complexity for TSO: Simulations by/of Lossy Channel Systems Decidability and complexity beyond TSO: ◮ Speculative writes lead to undecidability ◮ Decidability: deal with reordered reads A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 13 / 42

  4. The rest of the lecture Decidability and complexity for TSO: Simulations by/of Lossy Channel Systems Decidability and complexity beyond TSO: ◮ Speculative writes lead to undecidability ◮ Decidability: deal with reordered reads From TSO to SC under bounded analysis ◮ 2 notions of bounds ◮ Store buffers � 2K copies of the globals per thread A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 13 / 42

  5. An operational model for TSO Each process has a FIFO buffer Configuration = control states + memory state + buffers contents Write(x,d) is sent to the buffer Memory update = execution of a Write taken from some buffer Read(x,d) is executed either if ◮ The last Write to x in the buffer is Write(x,d) (Read Own Write) ◮ The buffer does not contain a Write to x , and Memory ( x ) = d AtomicRW ( x , d 1 , d 2 ) requires that the buffer is empty ( ∼ fence) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 14 / 42

  6. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 0 x 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  7. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  8. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  9. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) 1 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  10. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) 1 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  11. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) 1 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  12. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Model: The store buffers are considered as perfect FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) 1 The store buffer of Thread 1 y Deadlock A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 15 / 42

  13. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  14. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  15. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  16. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) w ( y , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  17. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) w ( y , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  18. From W → R systems to Lossy Channel Systems w(x , 1) w(y , 1) w(x , 2) w(y , 2) w(y , 3) p 0 p 1 p 2 p 3 p 4 p 5 Thread 1: r(x , 2) r(y , 0) q 0 q 1 q 2 Thread 2 : Assume that the store buffers are lossy FIFO channels 2 x w ( y , 3 ) w ( y , 2 ) w ( y , 1 ) 0 The store buffer of Thread 1 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 16 / 42

  19. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 y Channel= Sequence of memory states + Lossyness 0 x x = 2 x = 2 x = 2 x = 1 x = 1 y = 3 y = 2 y = 1 y = 1 y = 0 0 y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  20. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 y Channel= Sequence of memory states + Lossyness 0 x x = 2 x = 2 x = 2 x = 1 x = 1 y = 2 y = 1 y = 0 y = 3 y = 1 0 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  21. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 y Channel= Sequence of memory states + Lossyness 0 x x = 2 x = 2 x = 2 x = 1 x = 1 y = 2 y = 1 y = 0 y = 3 y = 1 0 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  22. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 0 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) w ( x , 1 ) 0 y Channel= Sequence of memory states + Lossyness 1 x x = 2 x = 2 x = 2 x = 1 y = 2 y = 1 y = 3 y = 1 0 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  23. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) 0 y Channel= Sequence of memory states + Lossyness 1 x x = 2 x = 2 x = 2 x = 1 y = 2 y = 1 y = 3 y = 1 0 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  24. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) w ( y , 1 ) 0 y Channel= Sequence of memory states + Lossyness 2 x x = 2 x = 2 x = 1 y = 2 y = 1 y = 3 1 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  25. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 1 x w ( y , 3 ) w ( y , 2 ) w ( x , 2 ) 1 y Channel= Sequence of memory states + Lossyness 2 x x = 2 x = 2 x = 1 y = 2 y = 1 y = 3 1 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  26. From W → R systems to Lossy Channel Systems Buffer = perfect FIFO channel 2 x w ( y , 3 ) w ( y , 2 ) 1 y Channel= Sequence of memory states + Lossyness 2 x x = 2 x = 2 x = 1 y = 2 y = 1 y = 3 1 y Lossyness= Unobservable memory states A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 17 / 42

  27. From W → R systems to Lossy Channel Systems Memory Process Write: Compute a new memory state; send it to the channel Read: Check the channel/memory Memory update: Receive a state; copy it to the memory A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 18 / 42

  28. From W → R systems to Lossy Channel Systems Problem: Interference between processes ? Memory Process Write: Compute a new memory state; send it to the channel Read: Check the channel/memory Memory update: Receive a state; copy it to the memory A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 18 / 42

  29. From W → R systems to Lossy Channel Systems Problem: Interference between processes ? ⇒ Each process guesses occurrences of writes by other processes Memory Process Write: Compute a new memory state; send it to the channel Read: Check the channel/memory Memory update: Receive a state; copy it to the memory Guessed Write: Send the guessed state to the channel A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 18 / 42

  30. From W → R systems to Lossy Channel Systems Problem: Interference between processes ? ⇒ Each process guesses occurrences of writes by other processes Memory Process Write: Compute a new memory state; send it to the channel Read: Check the channel/memory Memory update: Receive a state; copy it to the memory Guessed Write: Send the guessed state to the channel ⇒ Check that all process agree on the sequence of states Synchronization of the lossy channel machines over send actions A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 18 / 42

  31. Decidability for the State Reachability Problem Thm The state reachability problem for TSO programs is reducible to the control-state reachability problem for LCS. A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 19 / 42

  32. Decidability for the State Reachability Problem Thm The state reachability problem for TSO programs is reducible to the control-state reachability problem for LCS. Thm ([Abdulla, Jonsson, 1993]) The control-state reachability problem for LCS is decidable Corollary The state reachability problem for TSO systems is decidable. A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 19 / 42

  33. From Lossy Channel Systems to W → R systems write update T 1 x read read update write T 2 y T 1 simulates the lossy channel machine: ◮ Send operation: Write operation of T 1 to the variable x ◮ Read operation: Read operation of T 1 from the variable y T 2 transfers the successive values of the variable x to the variable y A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 20 / 42

  34. Complexity Thm Every LCS can be simulated by a TSO program. A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 21 / 42

  35. Complexity Thm Every LCS can be simulated by a TSO program. Thm ([Schnoebelen, 2001]) The control-state reachability problem for LCS is non-primitive recursive ⇒ Lower bound for the state reachability problem under TSO. A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 21 / 42

  36. TSO + R2W: Causality cycles x = y = 0 P 1 P 2 (1) r( x , 1) (3) r( y , 1) (2) w( y , 1) (4) w( x , 1) x = y = 1 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 22 / 42

  37. TSO + R2W: Causality cycles x = y = 0 P 1 P 2 (1) r( x , 1) (3) r( y , 1) (2) w( y , 1) (4) w( x , 1) x = y = 1 This behavior is possible since writes can overtake reads: (2) , (3) , (4) , (1) Speculative writes ⇒ causality cycles ◮ (2) is executed assuming that (1) will be executed in the future ◮ (1) is indeed executed, but it is based on a write that depends from (2) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 22 / 42

  38. TSO + R2W: Undecidabiity read v j 1 · · · v j m write u i 1 · · · u i n ♯ x 1 w ( x 1 , u i k ) w ( x 2 , v i l ) write i 1 · · · i n read j · · · j 1 ♯ r ( x 2 , u i k ) r ( x 1 , v i l ) r ( y 2 , i k ) m r ( y 1 , j l ) y 1 read u write v j 1 · · · v j m 1 · · · u ♯ i w ( y 1 , i k ) i w ( y 2 , j l ) read i 1 · · · i n n x 2 write j 1 · · · j m Thread 1 Thread 2 ♯ y 2 Assume that: u i 1 u i 2 · · · u i n = v j 1 v j 2 · · · v j m and i 1 i 2 · · · i n = j 1 j 2 · · · j m T 1 : r ( y 2 , i n ) w ( y 1 , i n ) r ( x 2 , u i n ) w ( x 1 , u i n ) · · · r ( y 2 , i 1 ) w ( y 1 , i 1 ) r ( x 2 , u i 1 ) w ( x 1 , u i 1 ) T 2 : r ( y 1 , j n ) w ( y 2 , j n ) r ( x 1 , v j n ) w ( x 2 , v j n ) · · · r ( y 1 , j 1 ) w ( y 2 , j 1 ) r ( x 1 , v j 1 ) w ( x 2 , v j 1 ) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 23 / 42

  39. TSO + R2W: Undecidabiity read v j 1 · · · v j m write u i 1 · · · u i n ♯ x 1 w ( x 1 , u i k ) w ( x 2 , v i l ) write i 1 · · · i n read j · · · j 1 ♯ r ( x 2 , u i k ) r ( x 1 , v i l ) r ( y 2 , i k ) m r ( y 1 , j l ) y 1 read u write v j 1 · · · v j m 1 · · · u ♯ i w ( y 1 , i k ) i w ( y 2 , j l ) read i 1 · · · i n n x 2 write j 1 · · · j m Thread 1 Thread 2 ♯ y 2 Assume that: u i 1 u i 2 · · · u i n = v j 1 v j 2 · · · v j m and i 1 i 2 · · · i n = j 1 j 2 · · · j m T 1 : r ( y 2 , i n ) r ( x 2 , u i n ) · · · r ( y 2 , i 1 ) r ( x 2 , u i 1 ) · · · w ( y 1 , i n ) w ( x 1 , u i n ) · · · w ( y 1 , i 1 ) w ( x 1 , u i 1 ) T 2 : w ( y 2 , j n ) w ( x 2 , v j n ) · · · w ( y 2 , j 1 ) w ( x 2 , v j 1 ) · · · r ( y 1 , j n ) r ( x 1 , v j n ) · · · r ( y 1 , j 1 ) r ( x 1 , v j 1 ) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 23 / 42

  40. TSO + R2W: Undecidabiity read v j 1 · · · v j m write u i 1 · · · u i n ♯ x 1 w ( x 1 , u i k ) w ( x 2 , v i l ) write i 1 · · · i n read j · · · j 1 ♯ r ( x 2 , u i k ) r ( x 1 , v i l ) r ( y 2 , i k ) m r ( y 1 , j l ) y 1 read u write v j 1 · · · v j m 1 · · · u ♯ i w ( y 1 , i k ) i w ( y 2 , j l ) read i 1 · · · i n n x 2 write j 1 · · · j m Thread 1 Thread 2 ♯ y 2 Assume that: u i 1 u i 2 · · · u i n = v j 1 v j 2 · · · v j m and i 1 i 2 · · · i n = j 1 j 2 · · · j m T 1 : r ( y 2 , i n ) r ( x 2 , u i n ) · · · r ( y 2 , i 1 ) r ( x 2 , u i 1 ) · · · w ( y 1 , i n ) w ( x 1 , u i n ) · · · w ( y 1 , i 1 ) w ( x 1 , u i 1 ) T 2 : w ( y 2 , j n ) w ( x 2 , v j n ) · · · w ( y 2 , j 1 ) w ( x 2 , v j 1 ) · · · r ( y 1 , j n ) r ( x 1 , v j n ) · · · r ( y 1 , j 1 ) r ( x 1 , v j 1 ) ⇒ Reachability TSO + R2W A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 23 / 42

  41. NSW: Non Speculative Writes TSO = Read-Local-Write-Early + W2R PSO = TSO + W2W NSW = PSO + R2R A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 24 / 42

  42. NSW: Non Speculative Writes TSO = Read-Local-Write-Early + W2R PSO = TSO + W2W NSW = PSO + R2R Simulation of TSO under PSO: Add a write-write fence ( wfence ) before each write A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 24 / 42

  43. NSW: Non Speculative Writes TSO = Read-Local-Write-Early + W2R PSO = TSO + W2W NSW = PSO + R2R Simulation of TSO under PSO: Add a write-write fence ( wfence ) before each write Simulation of PSO under NSW: Add a read-read fence ( rfence ) before each read A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 24 / 42

  44. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  45. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Configuration= control states + memory state + event structures p 0 x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  46. Operational Model: Event Structures w(x , 1) w(y , 1) wfence r(x , 2) w(y , 2) p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Writes on x are inserted after the last reads, wfences, and writes on x . p 1 w ( x , 1) x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  47. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Writes on y are inserted after the last reads, wfences, and writes on y . w ( y , 1) p 2 w ( x , 1) x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  48. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Wfences are inserted after the last writes. w ( y , 1) wf p 3 w ( x , 1) x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  49. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Reads on x are inserted after the last writes/reads on x . w ( y , 1) p 4 wf r ( x , 2) w ( x , 1) x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  50. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Writes on y are inserted after the last reads, wfences, and writes on y . w ( y , 2) w ( y , 1) p 5 wf r ( x , 2) w ( x , 1) x = 0 y = 0 q 0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  51. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Fences are performed by a process only when its event structure is empty. w ( y , 2) w ( y , 1) p 5 wf r ( x , 2) w ( x , 1) x = 0 y = 0 q 1 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  52. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Reads on y are inserted after the last writes/reads on y . w ( y , 2) w ( y , 1) p 5 wf r ( x , 2) w ( x , 1) x = 0 y = 0 q 2 r ( y , 1) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  53. Operational Model: Event Structures w(x , 1) w(y , 1) wfence r(x , 2) w(y , 2) p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Writes on x are inserted after the last reads, wfences, and writes on x . w ( y , 2) w ( y , 1) p 5 wf r ( x , 2) w ( x , 1) x = 0 y = 0 w ( x , 2) q 3 r ( y , 1) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  54. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Updates to memory are performed when those writes are minimal. w ( y , 2) p 5 wf r ( x , 2) w ( x , 1) x = 0 w ( x , 2) y = 1 q 3 r ( y , 1) A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  55. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Reads are validated w.r.t. the memory when they are minimal. w ( y , 2) p 5 wf r ( x , 2) w ( x , 1) x = 0 w ( x , 2) y = 1 q 3 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  56. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Rfences are performed by a process only if there is no pending reads. w ( y , 2) p 5 wf r ( x , 2) w ( x , 1) x = 0 w ( x , 2) y = 1 q 4 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  57. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: r(y , 1) w(x , 2) r(x , 2) fence rfence q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Reads on x are validated immediately with the last write on x (if possible) w ( y , 2) p 5 wf r ( x , 2) w ( x , 1) x = 0 w ( x , 2) y = 1 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  58. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Updates to memory are performed when those writes are minimal. w ( y , 2) p 5 wf r ( x , 2) x = 1 w ( x , 2) y = 1 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  59. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Updates to memory are performed when those writes are minimal. w ( y , 2) p 5 wf r ( x , 2) x = 2 y = 1 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  60. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Reads are validated w.r.t. the memory when they are minimal. w ( y , 2) p 5 wf x = 2 y = 1 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  61. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Wfences are removed if they are minimal. w ( y , 2) p 5 x = 2 y = 1 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  62. Operational Model: Event Structures w(x , 1) w(y , 1) r(x , 2) w(y , 2) wfence p 0 p 1 p 2 p 3 p 4 p 5 Process 1: fence r(y , 1) w(x , 2) rfence r(x , 2) q 0 q 1 q 2 q 3 q 4 q 5 Process 2: Updates to memory are performed when those writes are minimal. p 5 x = 2 y = 2 q 5 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 25 / 42

  63. From Event Structures to Buffers Event Structure Event Structure Store Buffer Semantics Semantics Semantics (without Reads) Read Elimination Wfence Elimination A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 26 / 42

  64. From Event Structures to Buffers Event Structure Event Structure Store Buffer Semantics Semantics Semantics (without Reads) Read Elimination Wfence Elimination A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 26 / 42

  65. Elimination of Reads Configuration= control states + event structures+ memory history buffer. w ( y , 1) p 0 wf wf w ( x , 3) w ( x , 2) w ( x , 1) x = 2 x = 2 x = 2 x = 2 x = 1 x = 0 w ( y , 1) y = 1 y = 1 y = 1 y = 0 y = 0 y = 0 q 0 wf P 1 : y P 2 : x , y P 1 : x w ( x , 2) Memory History Buffer A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 27 / 42

  66. From Event Structures to Buffers Event Structure Event Structure Store Buffer Semantics Semantics Semantics (without Reads) Read Elimination Wfence Elimination A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 28 / 42

  67. From Event Structures to Buffers Event Structure Event Structure Store Buffer Semantics Semantics Semantics (without Reads) Read Elimination Wfence Elimination A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 28 / 42

  68. Elimination of Write Fences Configurations= Control states + Variable/Serial Buffers + History Buffer w(x , 2) w(x , 1) p 0 w(y , 1) x = 0 y = 0 q 0 P 1 , P 2 : x , y Memory History Buffer Variable Buffers Serial Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 29 / 42

  69. The State Reachability Problem for NSW A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 30 / 42

  70. Decidability of State Reachability Approach: Well Structured Systems [Abdulla et al., Finkel et al.] Well-Quasi Ordering ≤ on Configurations on every sequence c 0 , c 1 , c 2 , . . . , ∃ i < j . c i ≤ c j Monotonicity: ≤ is a simulation relation w.r.t. transition relation of the model ⇒ Backward reachability analysis terminates Problem: NSW ? a c x=0 ⊲ ⊲ ⊲ x=0 b x=0 Sub-word ordering on buffers? � ◮ NSW are Not Monotonic! Hard to apply WSS framework to NSW a c x=0 ⊲ ⊲ ⊲ x=0 A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 31 / 42

  71. NSW + systems NSW ≡ NSW + NSW + : WSS wrt � w(x , 2) p 0 x = 1 x = 1 w(y , 0) x = 0 y = 1 y = 0 y = 0 q 0 P 2 : y P 1 : x P 1 , P 2 : x , y Single Serial Buffer Memory History Buffer Variable Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 32 / 42

  72. NSW + systems NSW ≡ NSW + Single Serial Buffer NSW + : WSS wrt � w(x , 2) p 0 x = 1 x = 1 w(y , 0) x = 0 y = 1 y = 0 y = 0 q 0 P 2 : y P 1 : x P 1 , P 2 : x , y Single Serial Buffer Memory History Buffer Variable Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 32 / 42

  73. NSW + systems Each message in the serial buffer NSW ≡ NSW + contains a snapshot of memory NSW + : WSS wrt � w(x , 2) p 0 x = 1 x = 1 w(y , 0) x = 0 y = 1 y = 0 y = 0 q 0 P 2 : y P 1 : x P 1 , P 2 : x , y Single Serial Buffer Memory History Buffer Variable Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 32 / 42

  74. NSW + systems NSW ≡ NSW + Unbounded buffers but lossy NSW + : WSS wrt � w(x , 2) p 0 x = 1 x = 1 w(y , 0) x = 0 y = 1 y = 0 y = 0 q 0 P 2 : y P 1 : x P 1 , P 2 : x , y Single Serial Buffer Memory History Buffer Variable Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 32 / 42

  75. NSW + systems Processes have different views NSW ≡ NSW + of memory (the use of pointers) NSW + : WSS wrt � w(x , 2) p 0 x = 1 x = 1 w(y , 0) x = 0 y = 1 y = 0 y = 0 q 0 P 2 : y P 1 : x P 1 , P 2 : x , y Single Serial Buffer Memory History Buffer Variable Buffers A. Bouajjani (LIAFA, UP7) Lecture 3: Weak Memory Models September 2012 32 / 42

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