La y out-Driven Logic Synthesis Based on Lattices Singapur, - - PowerPoint PPT Presentation

la y out driven logic synthesis based on lattices
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La y out-Driven Logic Synthesis Based on Lattices Singapur, - - PowerPoint PPT Presentation

La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 1 ' $ LA YOUT-DRIVEN SYNTHESIS F OR SUBMICRON TECHNOLOGY: MAPPING EXP ANSIONS TO REGULAR LA TTICES Ma rek A. P erk o wski, Edmund


slide-1
SLIDE 1 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 1 ' & $ % LA YOUT-DRIVEN SYNTHESIS F OR SUBMICRON TECHNOLOGY: MAPPING EXP ANSIONS TO REGULAR LA TTICES Ma rek A. P erk
  • wski,
Edmund Pierzchal a, and Rolf Drechsler +, Dept. Electr. Engn., P
  • rtland
State Universit y , P
  • rtland,
USA + Inst. Comp. Sci., Alb ert-Ludwigs-Universit y , F reiburg in Breisgau, Germany
slide-2
SLIDE 2 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 2 ' & $ % PLAN OF T ALK
  • Intro
duction
  • la
y
  • ut-driven
synthesis.
  • Expansions
and expansion no des.
  • Max-t
yp e versus LI-t yp e lattices.
  • Use
  • f
Shannon expansions to create a lattice.
  • SOP
expansions.
  • Regula
r la y
  • ut.
slide-3
SLIDE 3 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 3 ' & $ % MAIN IDEAS
  • Lattice
Structure
  • new
concept in VLSI la y
  • ut.
  • Applicati
  • ns
in submicron design, quantum devices, and designing new ne-grain FPGAs.
  • In
the regula r a rrangemen t
  • f
cells, every cell is connected to 4, 6
  • r
8 neighb
  • rs
and to vertical, ho rizontal and diagonal buses.
  • Metho
ds fo r expanding a rbitra ry bina ry and multi-valued combination al functions to this la y
  • ut
a re illustrated .
  • This
is a new app roach to la y
  • ut-driven
logic synthesis
  • f
combination al functions.
slide-4
SLIDE 4 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 4 ' & $ % BINARY DECION DIA GRAMS F OR SYMMETRIC FUNCTIONS
  • Expansions
  • f
functions, a re
  • p
erato rs that transfo rm a function to a few simpler functions.
  • F
  • r
instance, in canonical Shannon expansion function f is expanded with resp ect to input va riable a as follo ws: f = af a +
  • a
f
  • a
, where f a = f j a=1 , and f
  • a
= f j a=0 a re p
  • sitive
and negative cofacto rs
  • f
function f with resp ect to va riable a, resp ectively .
  • T
autological cofacto r functions a re combined to single no des.
  • No
des fo r functions f a and f
  • a
and bus fo r va riable a a re mapp ed to la y
  • ut,
and p ro cedure is rep eated fo r the next input va riable.
  • Any
single-output symmetrical bina ry function can b e directly mapp ed to regula r la y
  • ut
with 1,2,3,4,... no des in successive levels co rresp
  • nding
to input va riables.
slide-5
SLIDE 5 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 5 ' & $ % WHA T IF FUNCTION IS NOT SYMMETRIC?
  • W
e sho w hot to extend this app roach to a rbitra ry bina ry functions, not necessa rily symmetrical.
  • Other
expansions
  • f
functions can also b e used.
  • The
expansion no des a re mapp ed to neighb
  • rho
  • d
structures which a re mo re p
  • w
erful than those investigated theo reticall y in the past (Ak ers, Chrzano wsk a-Jesk e).
  • The
p rop
  • sed
here structures a re simila r to those from commercial Fine Grain FPGAs (A tmel
  • Concurrent
Logic, Xilinx
  • Algotronix,
Moto rola
  • Pilkington).
slide-6
SLIDE 6 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 6 ' & $ % THREE COMPONENTS OF LA TTICE DIA GRAMS
  • The
concept
  • f
a lattice diagram involves three comp
  • nents:
(A) Expansion
  • f
a no de function creates several successo r no des
  • f
this no de. F unction f co rresp
  • nds
to the initial no de in the lattice, initiall y a tree. (B) Joining
  • p
eration joins several no des
  • f
a b
  • ttom
  • f
the lattice (this level b efo re joinings lo
  • ks
lik e a tree). This is in a sense a reverse
  • p
eration to expansion. (3) Regula r geometry, to which the no des a re mapp ed, guides which no des
  • f
the level a re to b e joined.
slide-7
SLIDE 7 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 7 ' & $ % USE OF MUL TI-V ALUED LOGIC
  • Every
signal in the Lattice can b e treated as multi-valued (pa rticula rly , bina ry).
  • A
multivalue d (MV) connection fo r logic with 2 k values can b e realized b y k bina ry wires which comp rise a bus.
  • This
mak es the lattice "fat" and enco des the multi-value d signal to bina ry .
slide-8
SLIDE 8 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 8 ' & $ % SPECIAL CASES OF LA TTICE DIA GRAMS
  • Some
sp ecial cases
  • f
Lattice Diagrams a re theo retical mo dels
  • f
cellula r logic: { Ak ers Arra ys. { F at T rees, { Generali ze d PLAs, { Maitra cascades,
  • Another
sp ecial cases
  • f
Lattice Diagrams a re industria l structures from several patents
  • f
ne grain FPGAs (Moto rola, A tmel, Plessey , Pilkington) .
slide-9
SLIDE 9 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 9 ' & $ % OUR GENERALIZA TIONS
  • In
addition to structure, w e sho w constructive and ecient metho ds
  • f
designing discrete functions in these structures.
  • The
metho ds w ere also extended to continuous functions.
  • W
e sho w ed
  • n
many examples that this geometry is very p
  • w
erful and mo re universal than the p reviously investigated general cellula r structures.
  • Here
w e will further extend and unify these notions to expansions with mo re than 2 successo r functions, and geometries with mo re than 4 neighb
  • rs.
slide-10
SLIDE 10 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 10 ' & $ % EXP ANSION AND JOINING OPERA TIONS
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SLIDE 11 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 11 ' & $ %

afa a’ +a’g fa’b’ ab g a’ a a’ a b b’ b b’ b b’ f g a g fa’ a a’ +a’g ) a a’ +a’g b’(af ) +bfa’ b (af +b’ga a g +a g 0 a a fa1

1

(a)

f g

(b)

a0 a a a a a

1 1 2 2 2

+a ga a

1 1 2

fa a f

2

Figure 1: (a) Shannon, (b) T erna ry P
  • st.
slide-12
SLIDE 12 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 12 ' & $ % TYPES OF EXP ANSIONS
  • Tw
  • t
yp es
  • f
expansions: { maximum-t yp e, { Linea rly-In dep end ent (LI) t yp e.
  • Maximum-t
yp e expansions use the MAX gate (in bina ry logic
  • OR),
and disjoint literals
  • r
subfunctions fo r cofacto rs.
  • They
include bina ry Shannon (S) and Sum-of-Pro ducts (SOP) (P erk
  • wski
ULSI'97) expansions and their multiple-valu ed logic generaliza tion s, such as in P
  • st
logic.
  • Belo
w w e will p resent
  • nly
the maximum-t yp e expansions: Shannon, SOP , and P
  • st
(MV Shannon).
slide-13
SLIDE 13 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 13 ' & $ % ST AND ARD COF A CTORS VERSUS V-COF A CTORS
  • Each
bina ry function f is rep resented b y a pair [ON(f ),OFF(f )].
  • Thus
all cofacto rs f a fo r the p ro duct
  • f
literals a, a re pairs: f a = [ON(f a ),OFF(f a )].
  • Every
cofacto r f a
  • f
the p ro duct a
  • f
an (in)complete function f can b e interp reted as intersecting f with a and replacing all K-map cells
  • utside
p ro duct a with don't ca res.
  • A
standa rd cofacto r f x where x is a va riable do es not dep end
  • n
this va riable.
  • Our
cofacto r, vacuous cofacto r, denoted b y v-cofacto r, though, f x is still a function
  • f
all va riables including x, but as a result
  • f
cofacto ring the va riable x b ecomes vacuous.
slide-14
SLIDE 14 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 14 ' & $ % ST AND ARD COF A CTORS VERSUS V-COF A CTORS
  • Standa
rd cofacto rs a re in general not disjoint.
  • F
  • r
any t w
  • disjoint
p ro ducts a 1 and a 2 , the v-cofacto rs f a 1 and g a 2 a re disjoint.
  • Therefo
re functions f a 1 and g a 2 a re in an incomplete tautology relation, and functions f and g a re not changed when f a 1 and g a 2 a re joined (OR-ed) to create a new function: a 1 f a 1 + a 2 g a 2 , as in Fig. 1a (where: a 1 = a 2 = a, and
  • a
is denoted as a ).
  • This
w a y , the entire lattice is created level-b y-level , Fig. 1a.
  • F
unctions in lattice no des b ecome mo re and mo re unsp ecied when va riables in levels a re rep eated.
  • Ultimately
no des b ecome constants.
slide-15
SLIDE 15 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 15 ' & $ % ST AND ARD COF A CTORS VERSUS V-COF A CTORS. I I
  • Every
va riable cuts a Kmap into t w
  • disjoint
pa rts.
  • Thus,
a rbitra ry t w
  • functions
f and g can alw a ys b e expanded together to a Shannon lattice, with OR-ing as a join
  • p
eration, p rovided that: { the same va riable x i is used in the level, { and all expansions use negated literal
  • x
i in the left, and p
  • sitive
literal x i
  • f
the va riable in the right.
  • New
functions in levels a re created b y rea rranging the cofacto rs in joinings.
  • This
p ro cess can increase the numb er
  • f
no des in compa rison with a sha red OBDD
  • f
these functions.
  • But,
a regula r structure is created, thus simplifying la y
  • ut
and making dela ys p redictable.
  • In
case when the p ro ducts a 1 and a 2 a re not disjoint, the v-cofacto rs f a 1 and g a 2 can, in some cases, still fo rm an incomplete tautology
  • f
functions.
  • When
these t w
  • cofacto
rs satisfy a tautology relation, then functions f a 1 and g a 2 can b e joined (OR-ed) without changing functions f and g .
  • Obviously
, the same metho d w
  • rks
fo r a rbitra ry numb er
  • f
  • utput
functions.
slide-16
SLIDE 16 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 16 ' & $ % EXAMPLES OF REGULAR LA TTICES. I
slide-17
SLIDE 17 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 17 ' & $ %

a b c d a b b c c c d d d d e e e f f g d e e f g a d

(a) (b) (c) (d) (e) (f)

b c e f g a b c b d e g e h c e h 1 1 2

slide-18
SLIDE 18 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 18 ' & $ % EXAMPLES OF REGULAR LA TTICES. I I

Akers Array and standard 2x2 lattice

  • ne diagonal connection added

3x3 lattice,

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SLIDE 19 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 19 ' & $ % EXAMPLES OF REGULAR LA TTICES. I I I

a b c d a b b c c c d d d d e e e f f g d e e f g a d b c e f g Array without diagonal buses horizontal and vertical buses used for connections are not repeated Symmetric function, Variables on diagonals

slide-20
SLIDE 20 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 20 ' & $ % MUL TI-V ALUED SHANNON EXP ANSIONS AND JOININGS
  • The
metho d to create Shannon Lattices can b e easily expanded to MV Shannon expansions fo r multi-outpu t incomplete functions (see Fig. 1b).
  • In
terna ry logic, each single-va riabl e expansion cuts a function's map to three v-cofacto rs, and any t w
  • f
them can b e next recombined b y a joining
  • p
eration MAX
  • Fig.
1b.
  • MAX
is the maximum
  • p
eration denoted b y +.
  • Let
us
  • bserve
that disjointness
  • f
literals a ; a 1 ; a 2 is the fundamenta l condition that must b e satised to create maximum-t yp e lattices.
  • It
is a sp ecial case
  • f
Linea r Indep end enc e
  • f
functions used in LI expansions.
slide-21
SLIDE 21 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 21 ' & $ % SOP EXP ANSIONS
  • In
bina ry SOP expansions a b ranchin g from no de f is fo r any subset
  • f
literals l j that their union covers the no de function f . The SOP expansion is: f = l j f l j + l r f l r :::: + l s f l s .
  • The
metho d to create
  • rdered
Shannon lattices p resented ab
  • ve
can b e expanded to free (non-o rdered) Shannon Lattices and SOP Lattices.
  • Any
t w
  • no
des from the expansion that fo rm an incomplete tautology can b e joined as sho wn ab
  • ve.
  • S
and SOP expansion t yp es can b e mixed in levels, thus creating "pseudo" t yp e
  • f
lattices.
slide-22
SLIDE 22 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 22 ' & $ % LINEARL Y-INDEPENDENT EXP ANSIONS AND JOININGS
  • Linea
rly Indep endent expansions fo r bina ry case use EX OR gates.
  • Generalizations
  • f
Davio expansions.
  • F
  • r
nite multiple-valued logic they a re based
  • n
Galois Field Addition gate.
  • F
  • r
a rbitra ry algeb ras, they should have at least
  • ne
linea r (group)
  • p
eration.
  • Usually
based
  • n
the algeb raic structure
  • f
an a rbitra ry eld.
  • In
pa rticula r, they include: { S (OR can b e replaced with EX OR in Shannon expansion), { P
  • sitive
and Negative Davio (pD and nD, resp ectively), { general Linea rly Indep endent (bina ry and MV), { EX OR T erna ry expansions.
  • Joining
  • p
erations fo r these expansions a re mo re complicated.
slide-23
SLIDE 23 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 23 ' & $ % THE PROCESS OF LA TTICE CREA TION
  • One
level
  • f
function f is expanded to an assumed t yp e
  • f
the Lattice fo r a selected va riable (o r a group
  • f
va riables in case
  • f
LI expansion).
  • The
level
  • f
the tree is mapp ed to the assumed t yp e
  • f
Lattice.
  • This
means joining together some no des
  • f
the tree-lik e lo w er pa rt
  • f
the lattice.
  • The
p ro cedure requires rep eatin g some va riables in the lattice, the k ey p
  • int
w as thus to nd go
  • d
metho ds
  • f
va riable and expansion t yp es selections.
slide-24
SLIDE 24 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 24 ' & $ % THE PROCESS OF LA TTICE CREA TION. I I
  • One
app roach to the va riable
  • rder
and expansion t yp es selection is based
  • n
generalized pa rtial symmetries fo r cofacto rs.
  • W
e demonstrated that fo r real-life bina ry b enchma rk functions, and sta rting from the decomp
  • sition
al hiera rchy
  • f
pa rtitionin g va riables, the
  • verhead
  • f
va riable rep eatin g in plana ry lattices w as not excessive in each decomp
  • sed
blo ck.
  • This
is b ecause symmetric and nea rly symmetric blo cks a re p referred b y
  • ur
Curtis-lik e decomp
  • ser.
slide-25
SLIDE 25 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 25 ' & $ % OTHER REGULAR LA TTICES. I

1 2 2 3 3 4 1 2 2 3 3 3 4 4 4 4 5 5 5 5 6 6 6 1 b1 a1 a2 a0 b0 c0 d0 b1 b0 b2 c2 b2 b2 b0 b1 c0 c1 c0 c1 c2

a b c c b c d d d e e f d e d e d e d

c1

b c d c c e e d

a b c c c d b e g g e c e g

  • g’

e’

  • o

a b b c c

pD pD pD pD S S S S S S S S S S nD nD nD nD nD nD nD

c d b a

f1 f2 f3

(b) (a) (c) (d) (e) (f)

slide-26
SLIDE 26 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 26 ' & $ % BINARY LA TTICE WITH REPEA TED V ARIABLES IN DIA GONAL BUSES

a b b c c

slide-27
SLIDE 27 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 27 ' & $ % 3x3 LA TTICE, 3-OUTPUT FUNCTION, PSEUDO-KRONECKER

pD pD pD pD S S S S S S S S S S nD nD nD nD nD nD nD

c d b a

f1 f2 f3

slide-28
SLIDE 28 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 28 ' & $ %
slide-29
SLIDE 29 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 29 ' & $ %

b1 a1 a2 a0 b0 c0 d0 b1 b0 b2 c2 b2 b2 b0 b1 c0 c1 c0 c1 c2

a b c c b c d d d e e f d e d e d e d

c1

b c d c c e e d

Figure 2: T erna ry Lattice in Three-Dimension al Universe, and a w a y
  • f
slide-30
SLIDE 30 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 30 ' & $ % 2x2 fo
  • tnotesize
REGULAR LA YOUT GEOMETRIES
  • In
case
  • f
4 neighb
  • rs,
2x2 cells, the lattice is plana r and it is based
  • n
a rectangula r grid.
  • Cell
has t w
  • inputs
and t w
  • utputs.
  • The
structure generalizes the kno wn switch realizations
  • f
symmetric bina ry functions, based
  • n
Shannon expansion.
  • The
same structure fo r P
  • sitive
and Negative Davio expansions, negated va riables and constants as control va riables
  • f
the no des, no des controlled not b y va riables but b y functions, and inverted edges b et w een no des.
  • Lattice
diagram counterpa rts
  • f
Kroneck er, Pseudo-Kroneck er, and F ree Decision Diagrams.
  • Theo
rem Every non-symmetric function can b e symmetrized b y rep eating va riables.
slide-31
SLIDE 31 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 31 ' & $ %
  • The
selection
  • f
the next va riable explained using the Rep eated V a riable Maps.
  • Mo
dern technological realizations allo w to have mo re than
  • ne
control va riable in a level.
  • All
three t yp es
  • f
buses (vertical, ho rizontal and diagonal) a re used to lead any va riable to the circuit's levels.
slide-32
SLIDE 32 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 32 ' & $ % GENERALIZA TIONS TO 2x2 LA TTICE DIA GRAMS
  • Structures
without diagonal buses a re p
  • ssible.
  • Inputs
and
  • utputs
can
  • ccur
at avery p
  • int
inside the lattice.
  • P
airs
  • r
triplets
  • f
bina ry control va riables can b e used in no des.
  • Multivalued
controls can b e used.
  • F
  • r
a 4-neighb
  • r
lattice geometry , any canonical fo rm
  • f
Reed-Muller logic and its Linea rly Indep endent generalizations can b e realized.
  • Any
MV logic (fo r instance in GF(4)) can also b e realized in the 4-neighb
  • r
lattice, but this w
  • uld
  • ften
require many rep etitions
  • f
va riables.
  • Continuous
and fuzzy functions can also b e realized.
  • T
erna ry and quaterna ry lattices fo r bina ry , multiple-valued and continuous functions.
slide-33
SLIDE 33 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 33 ' & $ % 3x3 REGULAR LA YOUT GEOMETRIES
  • Every
cell has three inputs (from N, NE and E) and three
  • utputs
(to W, SW and S).
  • This
allo ws fo r realizati
  • ns
  • f:
{ generaliz ed terna ry diagrams (fo r bina ry EX OR logic). { a rbitra ry expansion-based P
  • st
logic. { GF(3) logic functions. { Any bina ry ,
  • r
MV logic can b e mapp ed as in the case
  • f
the 4-neighb
  • r
lattice, but no w la rger full trees a re mappable to subsets
  • f
lattices.
slide-34
SLIDE 34 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 34 ' & $ % 4x4 REGULAR LA YOUT GEOMETRIES
  • Every
cell has four inputs (from N,NE,NW, and E), and four
  • utputs
(to S, SW, SE, and W).
  • This
allo ws realizati
  • ns
  • f:
{ generaliz ed quaterna ry diagrams (fo r GF(4)), { a rbitra ry expansion-based P
  • st
  • r
GF(k), k < 4 functions. { Any bina ry
  • r
MV logic can b e mapp ed, and mo re eciently so.
slide-35
SLIDE 35 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 35 ' & $ % APPLICA TIONS OF LA TTICE DIA GRAMS
  • The
families
  • f
lattice diagrams w e intro duc ed a re counterpa rts and generalizati
  • ns
  • f
several diagrams kno wn from the literature (BDDs, FDDs, KFDDs).
  • Due
to this p rop ert y ,
  • ur
diagrams can p rovide a mo re compact rep resentation
  • f
functions than either
  • f
the standa rd decision diagrams, b ecause they do not require any placement
  • r
routing.
  • Placement
and routing come as a side-eect
  • f
logic synthesis.
  • Design
metho ds a re very ecient esp eciall y fo r strongly unsp ecied functions, the mo re unsp ecied the function, the b etter the results.
slide-36
SLIDE 36 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 36 ' & $ % CONCLUSION
  • New
metho ds intro duced ,
  • f
interest to deep sub-micron technology and pass-transisto r design fo r bina ry and MV gates.
  • sta
rting from all p
  • ssible
neighb
  • r
geometries in t w
  • and
three dimensiona l spaces, w e create all p
  • ssibl
e regula r structures.
  • This
extends p revious plana r geometries (Ak ers, Chrzano wsk a-Jesk e).
  • W
e design a rbitra ry expansions fo r the new structures.
  • New
expansions can b e constructed based
  • n
the Linea rly-Ind ep endent function theo ry ,
  • r
any
  • ther
canonical
  • r
non-canonica l function expansions.
  • There
exists a very high numb er
  • f
va rious new expansions.
slide-37
SLIDE 37 La y
  • ut-Driven
Logic Synthesis Based
  • n
Lattices Singapur, Septemb er 1997 37 ' & $ %
  • The
same, la y
  • ut-driven
synthesis app roaches a re created fo r bina ry , multivalue d, linea rly-inde p end ent , Galois and continuous functions.
  • The
p resented app roach generalizes and unies many kno wn expansions, decision diagrams, and regula r la y
  • ut
geometries.