La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 1 ' $ LA YOUT-DRIVEN SYNTHESIS F OR SUBMICRON TECHNOLOGY: MAPPING EXP ANSIONS TO REGULAR LA TTICES Ma rek A. P erk o wski, Edmund Pierzchal a, and Rolf Drechsler +, Dept. Electr. Engn., P o rtland State Universit y , P o rtland, USA + Inst. Comp. Sci., Alb ert-Ludwigs-Universit y , F reiburg in Breisgau, Germany & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 2 ' $ PLAN OF T ALK Intro duction - la y out-driven synthesis. � Expansions and expansion no des. � Max-t yp e versus LI-t yp e lattices. � Use of Shannon expansions to create a lattice. � SOP expansions. � Regula r la y out. � & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 3 ' $ MAIN IDEAS Lattice Structure - new concept in VLSI la y out. � Applicati ons in submicron design, quantum devices, and designing � new �ne-grain FPGAs. In the regula r a rrangemen t of cells, every cell is connected to 4, 6 � o r 8 neighb o rs and to vertical, ho rizontal and diagonal buses. Metho ds fo r expanding a rbitra ry bina ry and multi-valued � combination al functions to this la y out a re illustrated . This is a new app roach to la y out-driven logic synthesis of � combination al functions. & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 4 ' $ BINARY DECION DIA GRAMS F OR SYMMETRIC FUNCTIONS Expansions of functions, a re op erato rs that transfo rm a function to a � few simpler functions. F o r instance, in canonical Shannon expansion function f is expanded � with resp ect to input va riable a as follo ws: f = af a f , where + � � a a f f f f , and a re p ositive and negative cofacto rs of = = j j a =1 � a =0 a a f a , function with resp ect to va riable resp ectively . T autological cofacto r functions a re combined to single no des. � No des fo r functions f and f and bus fo r va riable a a re mapp ed to � � a a la y out, and p ro cedure is rep eated fo r the next input va riable. Any single-output symmetrical bina ry function can b e directly mapp ed � to regula r la y out with 1,2,3,4,... no des in successive levels co rresp onding to input va riables. & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 5 ' $ WHA T IF FUNCTION IS NOT SYMMETRIC? W e sho w hot to extend this app roach to a rbitra ry bina ry � functions, not necessa rily symmetrical. Other expansions of functions can also b e used. � The expansion no des a re mapp ed to neighb o rho o d structures � which a re mo re p o w erful than those investigated theo reticall y in the past (Ak ers, Chrzano wsk a-Jesk e). The p rop osed here structures a re simila r to those from commercial � Fine Grain FPGAs (A tmel - Concurrent Logic, Xilinx - Algotronix, Moto rola - Pilkington). & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 6 ' $ THREE COMPONENTS OF LA TTICE DIA GRAMS The concept of a lattice diagram involves three comp onents: � (A) Expansion of a no de function creates several successo r no des of this no de. F unction f co rresp onds to the initial no de in the lattice, initiall y a tree. (B) Joining op eration joins several no des of a b ottom of the lattice (this level b efo re joinings lo oks lik e a tree). This is in a sense a reverse op eration to expansion. (3) Regula r geometry , to which the no des a re mapp ed, guides which no des of the level a re to b e joined. & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 7 ' $ USE OF MUL TI-V ALUED LOGIC Every signal in the Lattice can b e treated as multi-valued � (pa rticula rly , bina ry). k A multivalue d (MV) connection fo r logic with values can b e 2 � realized b y k bina ry wires which comp rise a bus. This mak es the lattice "fat" and enco des the multi-value d signal � to bina ry . & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 8 ' $ SPECIAL CASES OF LA TTICE DIA GRAMS Some sp ecial cases of Lattice Diagrams a re theo retical mo dels � of cellula r logic: { Ak ers Arra ys. { F at T rees, { Generali ze d PLAs, { Maitra cascades, Another sp ecial cases of Lattice Diagrams a re industria l � structures from several patents of �ne grain FPGAs (Moto rola, A tmel, Plessey , Pilkington) . & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 9 ' $ OUR GENERALIZA TIONS In addition to structure, w e sho w constructive and e�cient � metho ds of designing discrete functions in these structures. The metho ds w ere also extended to continuous functions. � W e sho w ed on many examples that this geometry is very p o w erful � and mo re universal than the p reviously investigated general cellula r structures. Here w e will further extend and unify these notions to expansions � with mo re than 2 successo r functions , and geometries with mo re than 4 neighb o rs. & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 10 ' $ EXP ANSION AND JOINING OPERA TIONS & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 11 ' $ g f a a a’ a’ g fa’ afa +a’g a a’ b’ b b’ b b b’ g fa’b’ b’(af +a’g ) b (af +a’g ) ab (a) a a’ a a’ +bfa’ +b’ga g f 2 0 a 2 (b) a a a 0 a 1 1 a fa +a ga 1 g 0 a fa 1 1 +a g 0 a f 2 0 a 2 1 a 2 a (a) Shannon, (b) T erna ry P ost. Figure 1: & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 12 ' $ TYPES OF EXP ANSIONS Tw o t yp es of expansions: � { maximum-t yp e , { Linea rly-In dep end ent (LI) t yp e. Maximum-t yp e expansions use the MAX gate (in bina ry logic - � OR), and disjoint literals o r subfunctions fo r cofacto rs. They include bina ry Shannon (S) and Sum-of-Pro ducts (SOP) � (P erk o wski ULSI'97) expansions and their multiple-valu ed logic generaliza tion s, such as in P ost logic. Belo w w e will p resent only the maximum-t yp e expansions: � Shannon, SOP , and P ost (MV Shannon). & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 13 ' $ ST AND ARD COF A CTORS VERSUS V-COF A CTORS f [ON( f ),OFF( f Each bina ry function is rep resented b y a pair )]. � f a , Thus all cofacto rs fo r the p ro duct of literals a re pairs: � a f = [ON( f ),OFF( f )]. a a a Every cofacto r f of the p ro duct a of an (in)complete function f can � a b e interp reted as intersecting f with a and replacing all K-map cells a outside p ro duct with don't ca res. f x A standa rd cofacto r where is a va riable do es not dep end on this � x va riable. Our cofacto r, vacuous cofacto r , denoted b y v-cofacto r , though, f is � x still a function of all va riables including x , but as a result of cofacto ring the va riable x b ecomes vacuous. & %
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 14 ' $ ST AND ARD COF A CTORS VERSUS V-COF A CTORS Standa rd cofacto rs a re in general not disjoint. � F o r any t w o disjoint p ro ducts a and a , the v-cofacto rs f and � 1 2 a 1 g a re disjoint. a 2 Therefo re functions f and g a re in an incomplete tautology � a a 1 2 f g f g relation, and functions and a re not changed when and a a 1 2 a re joined (OR-ed) to create a new function: a f a g , as in Fig. 1a (where: a a a , and a is + = = � 1 a 2 a 1 2 1 2 denoted as a 0 ). This w a y , the entire lattice is created level-b y-level , Fig. 1a. � F unctions in lattice no des b ecome mo re and mo re unsp eci�ed � when va riables in levels a re rep eated. Ultimately no des b ecome constants. � & %
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