KAIROS: Incremental Verification in High-Level Synthesis through - PowerPoint PPT Presentation

ACM FMCAD, San Jose, USA KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design Luca Piccolboni, Giuseppe Di Guglielmo, and Luca P. Carloni Columbia University, NY, USA

High-Level Synthesis (HLS) Specification void void process( void void ) { int k = 0; int High-Level Synthesis for for (; k < 128; ++k) { // No unrolling c[k] = a[k] + b[k]; } } Area RTL Execution Time ACM FMCAD 2019, San Jose, USA 2 / 15

High-Level Synthesis (HLS) Specification void void process( void void ) { int k = 0; int High-Level Synthesis for for (; k < 128; k += 2) { // Manual unrolling Manual Code c[k+0] = a[k+0] + b[k+0]; Manipulations c[k+1] = a[k+1] + b[k+1]; } Area } RTL Execution Time ACM FMCAD 2019, San Jose, USA 2 / 15

High-Level Synthesis (HLS) Specification void void process( void void ) { int int k = 0; High-Level Synthesis for (; k < 128; ++k) for { HLS_LOOP_UNROLL(4); HLS Knobs c[k] = a[k] + b[k]; } } Area RTL Execution Time ACM FMCAD 2019, San Jose, USA 2 / 15

High-Level Synthesis (HLS) Specification void void process( void void ) { int k = 0; int High-Level Synthesis for for (; k < 128; ++k) { HLS_LOOP_UNROLL(10); c[k] = a[k] + b[k]; } } Area RTL Execution Time ACM FMCAD 2019, San Jose, USA 2 / 15

High-Level Synthesis (HLS) Specification void void process( void void ) { int int k = 0; High-Level Synthesis for for (; k < 128; ++k) { HLS_LOOP_UNROLL(10); How do we verify c[k] = a[k] + b[k]; } equivalence? } Area RTL Execution Time ACM FMCAD 2019, San Jose, USA 2 / 15

Equivalence Checking in HLS 1. Which notion of equivalence should we use? Latency-Insensitive Equivalence [L. P. Carloni, CAV’99] 2. How do we formally check the equivalence? KAIROS attacks this problem How do we verify equivalence? Area RTL Execution Time ACM FMCAD 2019, San Jose, USA 3 / 15

Latency-Insensitive Design (LID) Brief Introduction • LID separates computation from communication: a system is a set of computational processes that send and receive data through channels • The communication does not depend on the particular latencies of the channels • LID supports compositional design and verification (very useful for KAIROS!) [L. P. Carloni, CAV’99] ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data N bits FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface ? Producer Consumer Consumer Component #2 data FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data valid 1 FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data valid 0 FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data valid 1 ? FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data valid 1 ready FIFO FIFO 0 [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data valid 1 ready FIFO FIFO 1 [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) LI Interface Producer Consumer Consumer Component #2 data LI Interface valid ready FIFO FIFO [L. P. Carloni, CAV’99] FIFO ACM FMCAD 2019, San Jose, USA 4 / 15

Latency-Insensitive Design (LID) In High-Level Synthesis SC_MODULE M ready valid data LI Interface SC_MODULE N ACM FMCAD 2019, San Jose, USA 5 / 15

Latency-Insensitive Design (LID) In High-Level Synthesis SC_MODULE M { SC_MODULE M void process1( void ) { … handshake(); } LI Interface void process2( void ) { … handshake(); } ready valid data } LI Interface SC_MODULE N ACM FMCAD 2019, San Jose, USA 5 / 15

Latency-Insensitive Design (LID) In High-Level Synthesis SC_MODULE M { SC_MODULE M void process1( void ) { … handshake(); } LI Interface void process2( void ) { … handshake(); } ready valid data } LI Interface void process2( void ) { { HLS_REGION(“r1”); … } SC_MODULE N LI Interface { HLS_REGION(“r2”); … } } ACM FMCAD 2019, San Jose, USA 5 / 15

Latency-Insensitive Design (LID) Notion of Equivalence Definition: Two signals are equivalent if they present the same ordered sequence of values, but possibly with different timing 5 data_1 1 valid_1 MODULE #1 ready_1 1 data_2 5 valid_2 1 MODULE #2 ready_2 1 Increasing time ACM FMCAD 2019, San Jose, USA 6 / 15

Latency-Insensitive Design (LID) Notion of Equivalence Definition: Two signals are equivalent if they present the same ordered sequence of values, but possibly with different timing 5 5 5 8 data_1 1 0 0 1 valid_1 MODULE #1 ready_1 1 1 1 1 data_2 5 8 valid_2 1 1 MODULE #2 ready_2 1 1 Increasing time ACM FMCAD 2019, San Jose, USA 6 / 15

Latency-Insensitive Design (LID) Notion of Equivalence Definition: Two signals are equivalent if they present the same ordered sequence of values, but possibly with different timing 5 5 5 8 8 91 data_1 1 0 0 1 0 1 valid_1 MODULE #1 ready_1 1 1 1 1 1 1 8 91 91 91 data_2 5 8 91 valid_2 1 1 0 1 1 1 1 MODULE #2 ready_2 1 1 0 0 1 0 0 Increasing time ACM FMCAD 2019, San Jose, USA 6 / 15

Latency-Insensitive Design (LID) Notion of Equivalence Definition: Two signals are equivalent if they present the same ordered sequence of values ordered sequence of values, but possibly with different timing different timing 5 5 5 8 8 91 data_1 1 0 0 1 0 1 valid_1 MODULE #1 ready_1 1 1 1 1 1 1 8 91 91 91 data_2 5 8 91 valid_2 1 1 0 1 1 1 1 MODULE #2 ready_2 1 1 0 0 1 0 0 Increasing time ACM FMCAD 2019, San Jose, USA 6 / 15

Contributions KAIROS: Incremental Verification in High-Level Synthesis throughLatency-Insensitive Design SC_MODULE M1 SystemC High-Level Synthesis module IMP_1; … end module Verilog ACM FMCAD 2019, San Jose, USA 7 / 15

Contributions KAIROS: Incremental Verification in High-Level Synthesis throughLatency-Insensitive Design SC_MODULE M1 LI Interface SystemC High-Level Synthesis module IMP_1; LI Interface … end module Verilog ACM FMCAD 2019, San Jose, USA 7 / 15

Contributions KAIROS: Incremental Verification in High-Level Synthesis throughLatency-Insensitive Design 1 SC_MODULE M1 SC_MODULE M1* Manipulate the code LI Interface LI Interface SystemC SystemC High-Level Synthesis High-Level Synthesis module IMP_1; module IMP_2; LI Interface LI Interface … end module Verilog … end module Verilog ACM FMCAD 2019, San Jose, USA 7 / 15

Contributions KAIROS: Incremental Verification in High-Level Synthesis throughLatency-Insensitive Design 2 SC_MODULE M1 SC_MODULE M1* Modify the knobs Knobs LI Interface Knobs* LI Interface SystemC SystemC High-Level Synthesis High-Level Synthesis module IMP_1; module IMP_2; LI Interface LI Interface … end module Verilog … end module Verilog ACM FMCAD 2019, San Jose, USA 7 / 15

Contributions KAIROS: Incremental Verification in High-Level Synthesis throughLatency-Insensitive Design 2 SC_MODULE M1 SC_MODULE M1* Modify the knobs Knobs LI Interface Knobs* LI Interface SystemC SystemC High-Level Synthesis High-Level Synthesis module IMP_1; module IMP_2; EQUIVALENT? LI Interface LI Interface … end module Verilog … end module Verilog ACM FMCAD 2019, San Jose, USA 7 / 15

LID Compositionality SC_MODULE M SC_MODULE M void process1( void ) { void process1( void ) { { HLS_REGION(“r1*”); … } { HLS_REGION(“r1”); … } SystemC SystemC } } module M module M EQUIVALENT? module process1 module process1 module r1 ; … end module module r1* ; … end module Verilog Verilog … end module … end module ACM FMCAD 2019, San Jose, USA 8 / 15

LID Compositionality SC_MODULE M SC_MODULE M void process1( void ) { void process1( void ) { { HLS_REGION(“r1*”); … } { HLS_REGION(“r1”); … } SystemC SystemC } } module M module M module process1 module process1 module r1 ; … end module module r1* ; … end module EQUIVALENT? Verilog Verilog … end module … end module ACM FMCAD 2019, San Jose, USA 8 / 15

LID Compositionality [L. P. Carloni, CAV’99] Theorem: if we modify one module in a system, it is sufficient to prove the equivalence between the modified module and the original one to guarantee that the system functionality has not been affected by the modification. module M module M module process1 module process1 module r1 ; … end module module r1* ; … end module EQUIVALENT? LI Interface module r2 ; … end module module r2 ; … end module Verilog Verilog … end module … end module ACM FMCAD 2019, San Jose, USA 8 / 15