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Oct 19, 2023 298 likes •842 views

ACM FMCAD, San Jose, USA KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design Luca Piccolboni, Giuseppe Di Guglielmo, and Luca P. Carloni Columbia University, NY, USA High-Level Synthesis (HLS)

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SLIDE 1

KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design

Luca Piccolboni, Giuseppe Di Guglielmo, and Luca P. Carloni

Columbia University, NY, USA

ACM FMCAD, San Jose, USA

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SLIDE 2

2 / 15 ACM FMCAD 2019, San Jose, USA

High-Level Synthesis (HLS)

Specification High-Level Synthesis

void void process(void void) { int int k = 0; for for (; k < 128; ++k) { // No unrolling

c[k] = a[k] + b[k];

} }

RTL Area Execution Time

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SLIDE 3

2 / 15 ACM FMCAD 2019, San Jose, USA

High-Level Synthesis (HLS)

Specification High-Level Synthesis

void void process(void void) { int int k = 0; for for (; k < 128; k += 2) { // Manual unrolling

c[k+0] = a[k+0] + b[k+0]; c[k+1] = a[k+1] + b[k+1];

} }

Manual Code Manipulations RTL Area Execution Time

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SLIDE 4

2 / 15 ACM FMCAD 2019, San Jose, USA

High-Level Synthesis (HLS)

Specification High-Level Synthesis

void void process(void void) { int int k = 0; for for (; k < 128; ++k) { HLS_LOOP_UNROLL(4);

c[k] = a[k] + b[k];

} }

HLS Knobs RTL Area Execution Time

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SLIDE 5

2 / 15 ACM FMCAD 2019, San Jose, USA

High-Level Synthesis (HLS)

Specification High-Level Synthesis

void void process(void void) { int int k = 0; for for (; k < 128; ++k) { HLS_LOOP_UNROLL(10);

c[k] = a[k] + b[k];

} }

RTL Area Execution Time

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SLIDE 6

2 / 15 ACM FMCAD 2019, San Jose, USA

High-Level Synthesis (HLS)

Specification High-Level Synthesis

void void process(void void) { int int k = 0; for for (; k < 128; ++k) { HLS_LOOP_UNROLL(10);

c[k] = a[k] + b[k];

} }

RTL Area Execution Time

How do we verify equivalence?

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3 / 15 ACM FMCAD 2019, San Jose, USA

  • 1. Which notion of equivalence should we use?
  • 2. How do we formally check the equivalence?

KAIROS attacks this problem

Equivalence Checking in HLS

RTL Area Execution Time

How do we verify equivalence?

Latency-Insensitive Equivalence [L. P. Carloni, CAV’99]

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SLIDE 8

Latency-Insensitive Design (LID)

Brief Introduction

4 / 15

  • The communication does not depend on

the particular latencies of the channels

  • LID supports compositional design and

verification (very useful for KAIROS!)

[L. P. Carloni, CAV’99]

ACM FMCAD 2019, San Jose, USA

  • LID separates computation from communication:

a system is a set of computational processes that send and receive data through channels

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SLIDE 9

4 / 15

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

N bits

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data

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SLIDE 10

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data

?

4 / 15

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SLIDE 11

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data valid

1

4 / 15

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SLIDE 12

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data valid

4 / 15

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SLIDE 13

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data valid

1

4 / 15

?

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SLIDE 14

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data valid ready

1

4 / 15

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SLIDE 15

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

data valid ready

1 1

4 / 15

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SLIDE 16

Latency-Insensitive Design (LID)

ACM FMCAD 2019, San Jose, USA

FIFO Component #2

Consumer Producer Consumer data

FIFO

LI Interface

[L. P. Carloni, CAV’99]

FIFO

valid

LI Interface

ready

4 / 15

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SLIDE 17

ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

In High-Level Synthesis

data valid ready LI Interface

SC_MODULE M SC_MODULE N

5 / 15

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SLIDE 18

SC_MODULE M { }

5 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

In High-Level Synthesis

void process1(void) { … handshake(); } void process2(void) { … handshake(); }

data valid ready LI Interface

SC_MODULE N SC_MODULE M

LI Interface

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SLIDE 19

void process2(void) { }

5 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

In High-Level Synthesis

{ HLS_REGION(“r1”); … } { HLS_REGION(“r2”); … }

data valid ready LI Interface

SC_MODULE N SC_MODULE M SC_MODULE M { } void process1(void) { … handshake(); } void process2(void) { … handshake(); }

LI Interface LI Interface

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SLIDE 20

6 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

Notion of Equivalence

Definition: Two signals are equivalent if they present the same

  • rdered sequence of values, but possibly with different timing

MODULE

#1

data_1 valid_1 ready_1

MODULE

#2

data_2 valid_2 ready_2

1 1 1 1 5 5 Increasing time

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SLIDE 21

6 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

Notion of Equivalence

Definition: Two signals are equivalent if they present the same

  • rdered sequence of values, but possibly with different timing

data_1 valid_1 ready_1 data_2 valid_2 ready_2

1 1 1 1 5 5 8 8 1 1 1 1 1 5 5 1

MODULE

#1

MODULE

#2

Increasing time

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SLIDE 22

6 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

Notion of Equivalence

Definition: Two signals are equivalent if they present the same

  • rdered sequence of values, but possibly with different timing

data_1 valid_1 ready_1 data_2 valid_2 ready_2

1 1 1 1 5 5 8 91 8 1 1 1 1 1 1 1 5 5 8 1 1 91 1 1 1 1 1 8 91 91 91

MODULE

#1

MODULE

#2

Increasing time

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SLIDE 23

6 / 15 ACM FMCAD 2019, San Jose, USA

Latency-Insensitive Design (LID)

Notion of Equivalence

Definition: Two signals are equivalent if they present the same

  • rdered sequence of values, but possibly with different timing

data_1 valid_1 ready_1 data_2 valid_2 ready_2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

MODULE

#1

MODULE

#2

5 5 8 91 8 91 5 5 8 8 91 91 91 Increasing time

  • rdered sequence of values

different timing

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SLIDE 24

7 / 15 ACM FMCAD 2019, San Jose, USA

Contributions

SC_MODULE M1

SystemC

High-Level Synthesis

module IMP_1; … end module Verilog

High-Level Synthesis

KAIROS: Incremental Verification in throughLatency-Insensitive Design

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SLIDE 25

7 / 15 ACM FMCAD 2019, San Jose, USA

Contributions

SC_MODULE M1

SystemC

module IMP_1; … end module Verilog

High-Level Synthesis

KAIROS: Incremental Verification in throughLatency-Insensitive Design High-Level Synthesis

LI Interface LI Interface

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SLIDE 26

7 / 15 ACM FMCAD 2019, San Jose, USA

Contributions

SC_MODULE M1

SystemC

module IMP_1; … end module Verilog

High-Level Synthesis

KAIROS: Incremental Verification in throughLatency-Insensitive Design High-Level Synthesis

SC_MODULE M1*

SystemC

module IMP_2; … end module Verilog

High-Level Synthesis

Manipulate the code

1 LI Interface LI Interface LI Interface LI Interface

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SLIDE 27

7 / 15 ACM FMCAD 2019, San Jose, USA

Contributions

SC_MODULE M1

SystemC

module IMP_1; … end module Verilog

High-Level Synthesis

KAIROS: Incremental Verification in throughLatency-Insensitive Design High-Level Synthesis

SC_MODULE M1*

SystemC

module IMP_2; … end module Verilog

High-Level Synthesis

Modify the knobs

2

Knobs Knobs*

LI Interface LI Interface LI Interface LI Interface

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SLIDE 28

7 / 15 ACM FMCAD 2019, San Jose, USA

Contributions

SC_MODULE M1

SystemC

module IMP_1; … end module Verilog

High-Level Synthesis

KAIROS: Incremental Verification in throughLatency-Insensitive Design High-Level Synthesis

SC_MODULE M1*

SystemC

module IMP_2; … end module Verilog

High-Level Synthesis

Knobs*

EQUIVALENT?

Modify the knobs

2 LI Interface LI Interface

Knobs

LI Interface LI Interface

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SLIDE 29

8 / 15 ACM FMCAD 2019, San Jose, USA

LID Compositionality

SC_MODULE M void process1(void) { } { HLS_REGION(“r1”); … } SC_MODULE M void process1(void) { } { HLS_REGION(“r1*”); … }

SystemC SystemC

module M module process1 … end module

Verilog

module M module process1 … end module

Verilog

module r1; … end module module r1*; … end module

EQUIVALENT?

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8 / 15 ACM FMCAD 2019, San Jose, USA

LID Compositionality

SC_MODULE M void process1(void) { } { HLS_REGION(“r1”); … } SC_MODULE M void process1(void) { } { HLS_REGION(“r1*”); … }

SystemC SystemC

module M module process1 … end module

Verilog

module M module process1 … end module

Verilog

EQUIVALENT?

module r1; … end module module r1*; … end module

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8 / 15 ACM FMCAD 2019, San Jose, USA

LID Compositionality

module M module process1 … end module

Verilog

module M module process1 … end module

Verilog

module r2; … end module module r2; … end module

Theorem: if we modify one module in a system, it is sufficient to prove the equivalence between the modified module and the original one to guarantee that the system functionality has not been affected by the modification.

[L. P. Carloni, CAV’99]

EQUIVALENT?

module r1; … end module module r1*; … end module

LI Interface

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8 / 15 ACM FMCAD 2019, San Jose, USA

LID Compositionality

module M module process1 … end module

Verilog

module M module process1 … end module

Verilog

module r2; … end module module r2; … end module

Theorem: if we modify one module in a system, it is sufficient to prove the equivalence between the modified module and the original one to guarantee that the system functionality has not been affected by the modification.

[L. P. Carloni, CAV’99]

EQUIVALENT?

module r1; … end module module r1*; … end module

LI Interface

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SLIDE 33

equiv 9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

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SLIDE 34

equiv 9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

1 5 1

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SLIDE 35

equiv 9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

1 5 1

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SLIDE 36

equiv 9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

1 5 2 1 5 1

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SLIDE 37

9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

1 5 1 5 1 5 2 1

equiv

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SLIDE 38

9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

REGION

#1

REGION

#2

1 5 1 5 1 5 2 1

equiv

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SLIDE 39

9 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Checking Equivalence

  • ut_data_1
  • ut_valid_1
  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1 equiv

General Wrapper

MODEL CHECKER

always @(clk) equiv = 1

REGION

#1

REGION

#2

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SLIDE 40

10 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Improving Scalability

Observation: if region #1 is always faster than region #2, we can improve scalability by exploiting an equivalence checker

  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

SLOWER

Region

  • ut_data_1
  • ut_valid_1

FASTER

Region

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SLIDE 41

10 / 15 ACM FMCAD 2019, San Jose, USA

KAIROS: Improving Scalability

  • ut_data_2
  • ut_valid_2

in_data_1 in_valid_1

SLOWER

Region

  • ut_data_1
  • ut_valid_1
  • EQ. CHECKER

Optimized Wrapper

Observation: if region #1 is always faster than region #2, we can improve scalability by exploiting an equivalence checker

FASTER

Region

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SLIDE 42

11 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

Experimental Setup

  • HLS Tool: Cadence Stratus HLS
  • Eq. Tool: Cadence JasperGold
  • GRAY accelerator

We evaluated KAIROS on two case studies:

  • RISC-V processor

General Wrapper Optimized Wrapper

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SLIDE 43

12 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

GRAY Accelerator

R_0 R_1 G_0 G_1 B_0 B_1 G_0 G_1

input memories

ping-pong

  • utput memories

load proc. store proc.

  • comp. proc.

(memories 0)

  • comp. proc.

(memories 1)

40000 60000 80000 100000 120000 140000 160000 180000 150 200 250 300 350 400 450 500 550 600

REF UROL2 UROL4

Area (um2) Latency (ns)

UROL8 UROL16 UROL32

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SLIDE 44

12 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

GRAY Accelerator

40000 60000 80000 100000 120000 140000 160000 180000 150 200 250 300 350 400 450 500 550 600

REF UROL2 UROL4

Area (um2) Latency (ns)

UROL8 UROL16 UROL32

R_0 R_1 G_0 G_1 B_0 B_1 G_0 G_1

input memories

ping-pong

  • utput memories

load proc. store proc.

  • comp. proc.

(memories 0)

  • comp. proc.

(memories 1)

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SLIDE 45

12 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

GRAY Accelerator

40000 60000 80000 100000 120000 140000 160000 180000 150 200 250 300 350 400 450 500 550 600

REF UROL2 UROL4

Area (um2) Latency (ns)

UROL8 UROL16 UROL32

REF average time per property REF REF REF REF UROL2 UROL4 UROL8 UROL16 UROL32 22 min. 25 min. 28 min. 33 min. 33 min. UROL32 20 min. UROL16 64 properties

R_0 R_1 G_0 G_1 B_0 B_1 G_0 G_1

input memories

ping-pong

  • utput memories

load proc. store proc.

  • comp. proc.

(memories 0)

  • comp. proc.

(memories 1)

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SLIDE 46

12 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

GRAY Accelerator

40000 60000 80000 100000 120000 140000 160000 180000 150 200 250 300 350 400 450 500 550 600

REF UROL2 UROL4

Area (um2) Latency (ns)

UROL8 UROL16 UROL32 BUG#2 BUG#1

aggressive unrolling wrong

  • perator

REF time for counterexample REF BUG#1 BUG#2 1 min. 1 min.

More results in the paper

64 properties

R_0 R_1 G_0 G_1 B_0 B_1 G_0 G_1

input memories

ping-pong

  • utput memories

load proc. store proc.

  • comp. proc.

(memories 0)

  • comp. proc.

(memories 1)

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SLIDE 47

13 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

RISC-V Processor

[R. Margelli, Thesis 2017]

Data $$

  • Instr. $$

IF ID fedec M WB memwb EX exec

26000 26500 27000 27500 28000 200 250 300 350 400 450 500 Area (um2) Latency (ns)

REF PDIV1 UDIV4

SC_MODULE SC_MODULE SC_M.

process

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SLIDE 48

13 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

RISC-V Processor

26000 26500 27000 27500 28000 200 250 300 350 400 450 500 Area (um2) Latency (ns)

REF PDIV1 UDIV4 PDIV2 ARDIV

loop unrolling relax latency loop pipelining [R. Margelli, Thesis 2017]

Data $$

  • Instr. $$

IF ID fedec M WB memwb EX exec

SC_MODULE SC_MODULE SC_M.

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SLIDE 49

13 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

RISC-V Processor

26000 26500 27000 27500 28000 200 250 300 350 400 450 500 Area (um2) Latency (ns)

REF PDIV1 UDIV4 PDIV2 ARDIV

REF average time per property REF REF REF ARDIV PDIV1 PDIV2 UDIV4 33 min. 1 min. 1 min. 1 min. loop unrolling relax latency loop pipelining 11 properties [R. Margelli, Thesis 2017]

Data $$

  • Instr. $$

IF ID fedec M WB memwb EX exec

SC_MODULE SC_MODULE SC_M.

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SLIDE 50

13 / 15 ACM FMCAD 2019, San Jose, USA

Experimental Results

RISC-V Processor

26000 26500 27000 27500 28000 200 250 300 350 400 450 500 Area (um2) Latency (ns)

REF PDIV1 UDIV4 PDIV2 ARDIV

wrong loop condition REF time for counterexample REF BUG#1 BUG#2 1 min. 1 min.

BUG#1 BUG#2

wrong bit shifting

More results in the paper

11 properties [R. Margelli, Thesis 2017]

Data $$

  • Instr. $$

IF ID fedec M WB memwb EX exec

SC_MODULE SC_MODULE SC_M.

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SLIDE 51

14 / 15 ACM FMCAD 2019, San Jose, USA

Conclusions

We presented KAIROS a methodology for incremental verification of components developed with High-Level Synthesis (HLS) and Latency-Insensitive Design (LID)

  • KAIROS focuses on verifying the equivalence
  • f the RTL components designed with HLS
  • KAIROS exploits LID to reduce the amount of

code that must be checked for equivalence

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SLIDE 52

Speaker: Luca Piccolboni Columbia University, NY

Questions?

ACM FMCAD, San Jose, USA

KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design