Introduction to hardware design of block ciphers Francesco Regazzoni - - PowerPoint PPT Presentation

introduction to hardware design of block ciphers
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Introduction to hardware design of block ciphers Francesco Regazzoni - - PowerPoint PPT Presentation

Introduction to hardware design of block ciphers Francesco Regazzoni Francesco Regazzoni 20 October 2015, Chia, Italy P. 1 Contents 1 Hardware Design 2 ASIC 3 Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy P. 2


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Introduction to hardware design of block ciphers Francesco Regazzoni

Francesco Regazzoni 20 October 2015, Chia, Italy

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Contents

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Hardware Design

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ASIC

3

Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy

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Top-Down Approach From an high level specification (usually abstract) to detailed design by decomposition and successive refinement Answers to the question: “What do we build?” Handles the complexity

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Bottom-Up Approach From detailed primitive blocks to a larger and more complex functional block by combining primitives blocks Answers to the question: “How do we build it?” Focuses on the details Design usually proceed from both directions simultaneously

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Why Electronic Design Automation? Handle the complexity Design optimization Time to market

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Design Goals Speed Area Occupation Power Consumption Time to market Cost

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Speed Latency: time required to perform an action, measured in units of time (nanoseconds, clock periods, ...). Throughput: the number of such actions executed per unit of time, measured in units of what is being produced. Critical path: the path which creates longest delay Clock ≈

1 criticalpath

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Area Occupation Amount of silicon area occupied by the whole design

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Power Consumption Power = Current × Voltage, measured in Watt

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Power vs Energy Power = Current × Voltage, measured in Watt Energy = Power × Execution time, measured in Joule

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Time to Market and Cost Consumer electronic.... Non Recurring Engineering Costs

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Security?

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Contents

1

Hardware Design

2

ASIC

3

Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy

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Simplified Hardware Design Flow (ASIC)

Algorithm Design C, Matlab, VHDL

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Simplified Hardware Design Flow (ASIC)

Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL

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Simplified Hardware Design Flow (ASIC)

Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL Gate

x y x XOR y

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Simplified Hardware Design Flow (ASIC)

Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL Gate

x y x XOR y

Layout

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Standard Cell Library Library of Basic Gates (AND2x1, AND3x1, OR2X1...) Information about Logic function, power, area, timing Vertical and Horizontal Grid are defined All cells must have the same height

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Synthesis

RTL (Architecture) Design Synthesizable HDL Logic Synthesis Gate Level

x y x XOR y

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Definitions Logic Synthesis is the manipulation of logic specifications to create logic models as an interconnection of logic primitives Logic Synthesis determines the gate level structure of a circuit

From G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994.

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Logic Synthesis Input and Output INPUT: HDL Description Technological Library (function, area, timing, power, environmental constraints) Synthetic Library (multipliers...) Constraints OUTPUT: Gate Level Netlist Estimation of area, timing, power (!) Timing constraints

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Typical Logic Synthesis Steps

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State Minimization two State Encoding three Combinatorial Logic Minimization four Technology Mapping

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Place and Route

Gate

x y x XOR y

Place and Route Layout

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Place and Route Input and Output INPUT: Gate level description of the circuit Physical view of the library (pin placement, ...) Constraints from synthesis OUTPUT: Gate Level Netlist Position and interconnection of the gates Estimation of area, timing, power (!)

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This is not yet the end! PADs Design Rule Checks Layout vs Schematic Check Tape out

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Contents

1

Hardware Design

2

ASIC

3

Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy

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Reconfigurable Devices

Field Programmable Gate Arrays (FPGAs) Reconfigurable hardware devices Trade offs between ASIC and microprocessors Current progresses allow to store a complete SoC on FPGA

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Advantages of FPGA

Reduced non recurring engineering costs Reduced time to market Easier access to newer technologies

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High Level View

Configurable blocks (look-up-tables) Configurable routing matrix Input/Output blocks Memory configuration Advanced processing elements (DSP , whole processors)

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Simplified Hardware Design Flow (FPGAs)

HDL

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Simplified Hardware Design Flow (FPGAs)

HDL Synthesis

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Simplified Hardware Design Flow (FPGAs)

HDL Synthesis Place and route

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Simplified Hardware Design Flow (FPGAs)

HDL Synthesis Place and route Generate the bit stream

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Simplified Hardware Design Flow (FPGAs)

HDL Synthesis Place and route Generate the bit stream Burn the FPGA

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Hardware Design Final Remarks

Don’t compare apple with oranges!

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Questions? Thank you for your attention! mail: regazzoni@alari.ch

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