Introduction Exam aminers: ners: Markus us Trmnen nen (Anal - - PowerPoint PPT Presentation

ET ETIN35 IN35 & ETI & ETIN40 N40 – IC IC Pr Project

• ject 1 & 2

& 2

• IC Project 2014

Introduction

Exam aminers: ners: Markus us Törmänen nen (Anal alog+

• g+ Mixed)

ed) Joachi him m Rodrigues gues (Digital tal + C Computer uter)

IC Design Challenges

Limited ted bandwi dwidth dth Thermal mal noise Proces ess variat ations

• ns

Device nonlinear nearity ty Device e mismatc atch Limited ted model el accur urac acy Increased eased compl plex exity ty Slow simul ulations ations Crosstal talk Subs bstrat rate e noise A+D co-simul ulati ation

• n

An Analog alog An Analog alog Mi Mixed xed si signal gnal Mi Mixed xed si signal gnal

Supply pply noise

Large project

Time frame:

• Projects start now
• Circuits sent for fabrication: ~June 2014
• Circuits back for measurements: ~September 2014

Groups:

• 2-3 students per group

Important:

• Make & follow time-plan
• Systematic approach

Time plan bullets

• Literature search and studies
• System simulations
• Choice of circuit topologies, hand calculations
• Circuit simulations
• Layout work
• Measurements
• Writing of report (distributed)

Recommend 1 meeting/week with supervisor

Teaching Top Down Design Methodology through IC Design Projects Project ct input ut Pr Project ct execu cutio tion Pr Project ct examin inati ation

• n

Analog & Mixed IC Projects 2014 Rough Timeplan

• 2014 VT1 – System

tem model review ew. Study phase as well as designing and simulating a structural system stem model.

• 2014 end of VT1 – Schemat

atic c design review

• ew. Schemat

atic le level desig ign and simulations

• 2014 VT2 – Tape

Tape-Out Out design review ew. Layout ut and post layout simulations

• 2014 fall HT1-HT2

Measurement verification & design report rt

Requirements

• Passed Analog IC exam
• (Passed Digital IC exam)
• ETIN

IN35 5 - 7.5 .5 credits its:

– Design and implementation of a circuit prototype in UMC 130-nm CMOS – 3 Design reviews (project milestones) – Written design report

• ETIN

IN40 0 - 7.5 .5 credits its:

– Measurement verification & report

Project 1: Switched cap. regulated voltage doubler

Initial al Spec ecificati ations

• ns:

Vin 1.2V Vout(unloaded) 1.6V to 2.4V(50mV steps) Rout 10Ω clock frequency 2MHz Iload(max) 5mA Efficiency >90% Cpump 220nF(external) Cfilter 4.7uF(external)

Supervi rvised sed by Waqas s Ahmad or Mohamme mmed Abdulaziz laziz

Vin

phi2 phi1 phi2 phi1

Cpump Cfilter

Feedback DAC Non-

• verlap

+ Driver

phi1 phi2 vref

+

• clk_dbl

clk_in vout Latched comparator Off-chip capacitors MOS switches

vset<3:0>

Project 2: Ultra low-power clock generator

Initial al Spec ecificati ations

• ns:

Parameter value fin 1MHz fout 32MHz(N=32) Loop Bandwidth 100kHz Phase Noise

• 90dBc/Hz@250kHz

VDD 0.9V Current cosumption 40uA Division ratio (ndiv) 1, 16, 32, 64 dfin/dTemp(RC osc.) ±0.2% (-10C<Temp<60C)

Supervi rvised sed by Waqas s Ahmad or Mohamme mmed Abdulaziz laziz

/N

PFD

fout fin clk_ext RC_trim<n:0> ndiv<n:0> RC oscillator ref_sel

Project 3: Continuous Time ∆Σ Modulator

Supervised rvised by Xiaodo dong g Liu

• Reconfigurable for different bandwidth

– GSM: 200kHz – Bluetooth: 1MHz – WCDMA: 5MHz

• Reconfigurable Op-amp for power saving
• Multi-bit quantizer + DAC
• Dynamic element matching, e.g. DWA

Apply for a project now!

Talk to the superviso rvisors rs:

• Waqas

s Ahmad

• Mohammed

med Abdulaziz aziz

• Xiaodong

ng Liu

• r to the course

rse manager ger Marku rkus s Törmän änen en

Participants

• t