introduction: LDMOS devices gate B/S D Low-voltage n+ n+ p+ - - PowerPoint PPT Presentation
TU / e Compact Modelling of LDMOS Devices A.C.T. Aarts, R. van der Hout, R. van Langevelde, A.J. Scholten, M.B. Willemsen and D.B.M. Klaassen Philips Research Eindhoven University of Laboratories, Technology, The Netherlands The
A.C.T. Aarts, R. van der Hout,
M.B. Willemsen and D.B.M. Klaassen
Laboratories, The Netherlands
Eindhoven University of Technology, The Netherlands
Low-voltage
B/S D
buried oxide (box) p-well n+ p+ n- drift region gate n+
introduction: LDMOS devices
introduction: LDMOS devices
Low-voltage
B/S D
buried oxide (box) p-well n+ p+ n- drift region gate n+
High-voltage
B/S D
buried oxide (box) p-well n+ p+ n- drift region gate n+ LOCOS
introduction: LDMOS devices
LDMOS applications ⇒ ⇒ ⇒ ⇒ accurate modelling important
LDMOS
Pout [ Watt ] GT [ dB ] IMD3 [ dBc ] @ 2.2 GHz
RF-power amplifiers
modelling approach: sub-circuit models
G
channel region
D S
drift region
B
modelling approach: sub-circuit models
G
channel region
D S
MM31 MM11
drift region
B
modelling approach: sub-circuit models
G
channel region
D S
pro’s
channel / drift region
MM31 MM11
drift region
B
modelling approach: sub-circuit models
G
channel region
D S
pro’s
channel / drift region
con’s
convergence
MM31 MM11
drift region
B
modelling approach: single models
G D S B
modelling approach: single models
G D S B
MOS Model 20
modelling approach: single models
pro’s
G D S B
MOS Model 20
modelling approach: single models
con’s
channel / drift region
pro’s
G D S B
MOS Model 20
– DC-model
– nodal charge model
MOS Model 20: DC-model
n+ p p+
B S G Di
n+ n-
D
Continuity eq: Ich = Idr
MOS Model 20: DC-model
n+ p p+
B S G Di
n+ n-
D
Ich = Ich (VDiS, VGS, VSB)
MOS Model 20: DC-model
n+ p p+
S G Di
n+ n-
D B Idr = Idr (VGDi , VGD , VDiB)
MOS Model 20: DC-model
Ich (VDiS, VGS, VSB) = Idr (VDiS, VDS , VGS , VSB)
internal node Di expressed analytically from
n+ p p+
B S G Di
n+ n-
D
MOS Model 20: DC-model
G D S B
IDS = Ich (ψ ψ ψ ψsL, ψ ψ ψ ψs0) ψ ψ ψ ψs0 = ψ ψ ψ ψs0 (VSB, VGB) ψ ψ ψ ψsL = ψ ψ ψ ψsL (VDiB, VGB) surface-potential based
MOS Model 20: DC-model
G D S B
– DC-model
– nodal charge model
MOS Model 20: experimental data
IDS [ mA ]
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC VDS = 8.1V VDS = 0.1V
VSB=0V VSB=1V VSB=2V
3 2 1
VGS [ V ]
MOS Model 20: experimental data
VSB = 0V VSB = 1V VSB = 2V
2 4 6 8 10 12
VGS [ V ]
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.3 0.4
IDS [ mA ]
VDS=0.1 V
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC
MOS Model 20: experimental data
2 4 6 8 10 12
VGS [ V ]
0.02 0.04 0.06 0.08 0.10
gm [ mA/V ]
VSB = 0V VSB = 1V VSB = 2V
2 4 6 8 10 12
VGS [ V ]
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.3 0.4
IDS [ mA ]
VDS=0.1 V
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC
MOS Model 20: experimental data
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC 2 4 6 8
IDS [ mA ]
2 4 6 8 10
VDS [ V ]
VGS = 6V VGS = 12V VGS = 9V VGS = 3V VSB=0 V
MOS Model 20: experimental data
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC 2 4 6 8
IDS [ mA ]
2 4 6 8 10
VDS [ V ]
VGS = 6V VGS = 12V VGS = 9V VGS = 3V VSB=0 V
2 4 6 8 10
VDS [ V ]
10-7 10-6 10-5 10-4 10-3 10-2
|gDS| [ mA/V ]
MOS Model 20: experimental data
12V SOI-LDMOS: Tox= 38 nm, W= 17 µ µ µ µm, L= 1.6 µ µ µ µm, T= 25 oC 2 4 6 8
IDS [ mA ]
2 4 6 8 10
VDS [ V ]
VGS = 6V VGS = 12V VGS = 9V VGS = 3V VSB=0 V
2 4 6 8 10
VDS [ V ]
10-7 10-6 10-5 10-4 10-3 10-2
|gDS| [ mA/V ]
negative due to self-heating
– DC-model
– nodal charge model
MOS Model 20: nodal charge model
n+ p p+
B S G Di
n+ n-
D
MOS Model 20: gate and bulk charges
( ( ( ( ) ) ) )
⋅ ⋅ ⋅ ⋅ + + + + + + + + − − − − = = = =
L
dx Q Q Q W Q
' acc ' dep ' inv channel G,
( ( ( ( ) ) ) )
⋅ ⋅ ⋅ ⋅ + + + + = = = =
L
dx Q Q W Q
' acc ' dep channel B,
n+ p p+
B S G Di
n+ n-
D
( ( ( ( ) ) ) )
⋅ ⋅ ⋅ ⋅ + + + + + + + + − − − − = = = =
dr
' acc ' dep ' inv region drift G, L
dx Q Q Q W Q
⋅ ⋅ ⋅ ⋅ = = = =
dr
' inv region drift B, L
dx Q W Q
MOS Model 20: gate and bulk charges
n+ p p+
S G Di
n+ n-
D B
region drift G, channel G, LDMOS G,
Q Q Q + + + + = = = =
region drift B, channel B, LDMOS B,
Q Q Q + + + + = = = =
MOS Model 20: gate and bulk charges
n+ p p+
B S G Di
n+ n-
D
region drift G, channel G, LDMOS G,
Q Q Q + + + + = = = =
region drift B, channel B, LDMOS B,
Q Q Q + + + + = = = =
( ( ( ( ) ) ) )
j i ij ij
1 2 V Q C ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ⋅ ⋅ ⋅ ⋅ − − − − ⋅ ⋅ ⋅ ⋅ = = = = δ δ δ δ
MOS Model 20: gate and bulk charges
n+ p p+
B S G Di
n+ n-
D
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
CGG [ fF ]
3 6 9 12
VGS [ V ]
80 120 160 200
measurements MM9 + MM31 MOS M0del 20
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
CGG [ fF ]
3 6 9 12
VGS [ V ]
80 120 160 200
measurements MM9 + MM31 MOS M0del 20
CGD [ fF ]
VGS = 9V VGS = 5V
2 4 6 8 10 12 14
VDS [ V ]
VGS = 7V 140 120 100 80 60 40 20
MOS Model 20: source and drain charges
acc inv
S D
+ + + +
+ + + + + + + + + + + + = = = =
L L L L
dx Q L L x W dx Q L L x W Q
dr
' acc dr ' inv dr LDMOS D,
+ + + +
+ + + + − − − − + + + + + + + + + + + + − − − − + + + + = = = =
L L L L
dx Q L L x L L W dx Q L L x L L W Q
dr
' acc dr dr ' inv dr dr LDMOS S,
Ward-Dutton (uniform MOSFET)
channel region in strong inversion
MOS Model 20: source and drain charges
+
=
dr
' acc LDMOS D, L L L
dx Q W Q
S D
acc
channel region in weak inversion
=
LDMOS S,
Q all charge in the drift region attributed to the drain
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
CDD [ fF ]
160 120 80 40
VGS = 9V VGS = 5V
2 4 6 8 10 12 14
VDS [ V ]
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
CDD [ fF ]
160 120 80 40
VGS = 9V VGS = 5V
2 4 6 8 10 12 14
VDS [ V ]
3 6 9 12
VGS [ V ] fT [ GHz ]
2.0 1.5 1.0 0.5
VDS = 5V VDS = 14V VDS = 1V
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
3 6 9 12
VGS [ V ]
CDG [ fF ]
160 120 80 40 200 VDS = 5V VDS = 1V VDS = 0V
MOS Model 20: experimental data
14V SOI-LDMOS: Tox= 60 nm, W= 50 µ µ µ µm, L= 5 µ µ µ µm, T= 25 oC
3 6 9 12
VGS [ V ]
CDG [ fF ]
160 120 80 40 200 VDS = 5V VDS = 1V VDS = 0V diffused doping in channel region
– DC-model
– nodal charge model
High-voltage
B/S D
buried oxide (box) p-well n+ p+ n- drift region gate n+ LOCOS
saturation may occur in drift region
quasi-saturation
quasi-saturation
G D B/S MM 20 new MM 20: includes quasi-saturation
n+ p p+
B S G Di
n+ n-
D
quasi-saturation
n+ p p+
S G Di
n+ n-
D B
quasi-saturation
n+ p p+
S G Di
n+ n-
D B
quasi-saturation
eff DDi, drift 3 eff drift
V ⋅ + = θ µ µ 1
sat drift eff
drift
v L ⋅ ⋅ ⋅ ⋅ = = = = µ µ µ µ θ θ θ θ 3
Ldrift
High-voltage
B/S D
buried oxide (box) p-well n+ p+ n- drift region gate n+ LOCOS
sub-circuit
quasi-saturation
60V SOI-LDMOS: Tox= 38nm, W= 20µ µ µ µm, L= 2.6µ µ µ µm, Llocos= 3.5µ µ µ µm, T= 25 oC
IDS [ mA ]
10 8 6 4 2 2 6 8 12
VDS [ V ]
4 10
drift region without saturation VGS=2.4V VGS=3.4V VGS=4.4V VGS=6V VGS=8V VGS=10V VGS=12V
quasi-saturation
60V SOI-LDMOS: Tox= 38nm, W= 20µ µ µ µm, L= 2.6µ µ µ µm, Llocos= 3.5µ µ µ µm, T= 25 oC
IDS [ mA ]
10 8 6 4 2 2 6 8 12
VDS [ V ]
4 10
IDS [ mA ]
10 8 6 4 2 2 6 8 12
VDS [ V ]
4 10
drift region without saturation drift region with saturation VGS=2.4V VGS=3.4V VGS=4.4V VGS=6V VGS=8V VGS=10V VGS=12V
quasi-saturation
summary
MOS Model 20
by inclusion of quasi-saturation
to sub-circuit model
documentation
“A surface-potential-based high-voltage compact LDMOS transistor model”, IEEE Trans. Electron Devices, Vol. 52, No. 5, 2005
“Compact modeling of High-Voltage LDMOS Devices including quasi-saturation”, IEEE Trans. Electron Devices, Vol. 53, No. 4, 2006
www.semiconductors.philips.com/Philips_Models