introduction: LDMOS devices gate B/S D Low-voltage n+ n+ p+ - PowerPoint PPT Presentation

TU / e � Compact Modelling of LDMOS Devices A.C.T. Aarts, R. van der Hout, R. van Langevelde, A.J. Scholten, M.B. Willemsen and D.B.M. Klaassen Philips Research Eindhoven University of Laboratories, Technology, The Netherlands The Netherlands

introduction: LDMOS devices gate B/S D Low-voltage n+ n+ p+ p-well n - drift region buried oxide (box)

introduction: LDMOS devices gate B/S D Low-voltage n+ n+ p+ p-well n - drift region buried oxide (box) gate B/S D LOCOS High-voltage n+ n+ n - drift region p+ p-well buried oxide (box)

introduction: LDMOS devices RF-power amplifiers @ 2.2 GHz IMD 3 [ dBc ] G T [ dB ] LDMOS P out [ Watt ] LDMOS applications ⇒ ⇒ accurate modelling ⇒ ⇒ important

modelling approach: sub-circuit models G drift region channel region D S B

modelling approach: sub-circuit models G drift region channel region MM11 MM31 D S B

modelling approach: sub-circuit models G drift region channel region MM11 MM31 D S B pro’s • flexible • charge partitioning channel / drift region

modelling approach: sub-circuit models G drift region channel region MM11 MM31 D S B con’s pro’s • flexible • uncontrolled node • computation time / • charge partitioning channel / drift region convergence

modelling approach: single models G D S B

modelling approach: single models G MOS Model 20 D S B

modelling approach: single models G MOS Model 20 D S B pro’s • no uncontrolled node • convergence

modelling approach: single models G MOS Model 20 D S B pro’s con’s • no uncontrolled node • charge partitioning • convergence channel / drift region

outline • introduction • MOS Model 20 – DC-model • comparison with experimental data – nodal charge model • quasi-saturation • summary

MOS Model 20: DC-model G D B S n+ n+ p+ Di p n- Continuity eq: I ch = I dr

MOS Model 20: DC-model G D B S n+ n+ p+ Di I ch = I ch ( V DiS , V GS, V SB ) p n- • strong inversion • mobility reduction due to vertical field • velocity saturation

MOS Model 20: DC-model G D S I dr = I dr ( V GDi , V GD , V DiB ) n+ n+ p+ B Di p n- • accumulation • depletion • bulk current • mobility reduction due to vertical field

MOS Model 20: DC-model G D B S n+ n+ p+ Di p n- internal node Di expressed analytically from I ch ( V DiS , V GS, V SB ) = I dr ( V DiS , V DS , V GS , V SB )

MOS Model 20: DC-model G surface-potential based D S I DS = I ch ( ψ ψ sL , ψ ψ s0 ) ψ ψ ψ ψ ψ s0 = ψ ψ ψ ψ ψ ψ s0 ( V SB , V GB ) ψ B ψ ψ sL = ψ ψ ψ ψ sL ( V DiB , V GB ) ψ ψ • weak and strong inversion • saturation in channel region • accumulation and bulk current in drift region • mobility reduction • DIBL and static feedback • weak avalanche

MOS Model 20: DC-model G D S B • 21 dc-parameters • temperature scaling (6 parameters) • self-heating • width-scaling • length scaling

outline • introduction • MOS Model 20 – DC-model • comparison with experimental data – nodal charge model • quasi-saturation • summary

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ µ m, L = 1.6 µ µ µ µ V DS = 8.1V V DS = 0.1V I DS [ mA ] V SB =0V V SB =1V V SB =2V 2 1 3 V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ µ m, L = 1.6 µ µ µ µ I DS [ mA ] 0.4 V SB = 0V 0.3 V SB = 1V V SB = 2V 0.2 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V DS =0.1 V 0 0 2 4 6 8 10 12 V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ m, L = 1.6 µ µ µ µ µ I DS [ mA ] g m [ mA/V ] 0.10 0.4 V SB = 0V 0.08 0.3 V SB = 1V 0.06 V SB = 2V 0.2 0.04 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.02 V DS =0.1 V 0 0 0 2 4 6 8 10 12 0 2 4 6 8 10 12 V GS [ V ] V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ µ m, L = 1.6 µ µ µ µ I DS [ mA ] 8 V GS = 12V V SB =0 V 6 V GS = 9V 4 V GS = 6V 2 V GS = 3V 0 0 2 4 6 8 10 V DS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ µ m, L = 1.6 µ µ µ µ I DS [ mA ] |g DS | [ mA/V ] 10 -2 8 V GS = 12V V SB =0 V 10 -3 6 V GS = 9V 10 -4 4 V GS = 6V 10 -5 2 10 -6 V GS = 3V 10 -7 0 0 2 4 6 8 10 0 2 4 6 8 10 V DS [ V ] V DS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 12V SOI-LDMOS: T ox = 38 nm, W = 17 µ µ µ m, L = 1.6 µ µ µ µ I DS [ mA ] |g DS | [ mA/V ] 10 -2 8 negative due to V GS = 12V V SB =0 V self-heating 10 -3 6 V GS = 9V 10 -4 4 V GS = 6V 10 -5 2 10 -6 V GS = 3V 10 -7 0 0 2 4 6 8 10 0 2 4 6 8 10 V DS [ V ] V DS [ V ]

outline • introduction • MOS Model 20 – DC-model • comparison with experimental data – nodal charge model • quasi-saturation • summary

MOS Model 20: nodal charge model G D B S n+ n+ p+ Di p n-

MOS Model 20: gate and bulk charges G D B S n+ n+ p+ Di p n- L ( ( ) ) ( ( ) ) ∫ ∫ ∫ ∫ ' ' ' = = − − + + + + ⋅ ⋅ Q = = − − W Q + + Q + + Q ⋅ ⋅ dx G, channel inv dep acc 0 L ( ( ( ( ) ) ) ) ∫ ∫ ∫ ∫ ' ' Q = = = = W Q + + + + Q ⋅ ⋅ ⋅ ⋅ dx B, channel dep acc 0

MOS Model 20: gate and bulk charges G D S n+ n+ p+ B Di p n- L dr ( ( ( ( ) ) ) ) ∫ ∫ ∫ ∫ ' ' ' Q = = = = − − − − W Q + + + + Q + + + + Q ⋅ ⋅ ⋅ ⋅ dx G, drift region inv dep acc 0 L dr ∫ ∫ ∫ ∫ ' Q = = = = W Q ⋅ ⋅ ⋅ ⋅ dx B, drift region inv 0

MOS Model 20: gate and bulk charges G D B S n+ n+ p+ Di p n- Q = = = = Q + + + + Q G, LDMOS G, channel G, drift region Q = = = = Q + + + + Q B, LDMOS B, channel B, drift region

MOS Model 20: gate and bulk charges G D B S n+ n+ p+ Di p n- Q = = = = Q + + + + Q G, LDMOS G, channel G, drift region ∂ ∂ ∂ ∂ Q ( ( ) ) ( ( ) ) i C = = = = 2 ⋅ ⋅ ⋅ ⋅ δ δ δ δ − − − − 1 ⋅ ⋅ ⋅ ⋅ ij ij ∂ ∂ ∂ ∂ V j Q = = = = Q + + + + Q B, LDMOS B, channel B, drift region

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C GG [ fF ] 200 160 120 measurements MM9 + MM31 80 MOS M0del 20 - 6 - 3 0 3 6 9 12 V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C GG [ fF ] C GD [ fF ] 200 140 120 V GS = 7V 160 100 80 V GS = 9V 120 60 measurements 40 MM9 + MM31 V GS = 5V 80 MOS M0del 20 20 0 - 6 - 3 0 3 6 9 12 0 2 4 6 8 10 12 14 V GS [ V ] V DS [ V ]

MOS Model 20: source and drain charges acc inv S D channel region in strong inversion Ward-Dutton (uniform MOSFET) L + + + + L L dr x x ∫ ∫ ∫ ∫ ∫ ∫ ∫ ∫ ' ' Q = = = = W Q dx + + + + W Q dx D, LDMOS inv acc + + + + L + + L L + + L dr dr 0 L L + + + + L L dr L + + + + L − − − − x L + + + + L − − − − x ∫ ∫ ∫ ∫ ∫ ∫ ∫ ∫ dr ' dr ' Q = = = = W Q dx + + + + W Q dx S, LDMOS inv acc + + + + L + + L L + + L dr dr L 0

MOS Model 20: source and drain charges acc S D channel region in weak inversion all charge in the drift region attributed to the drain + L L dr ∫ ' Q = W Q dx D, LDMOS acc L Q = 0 S, LDMOS

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C DD [ fF ] 160 V GS = 5V 120 80 V GS = 9V 40 0 0 2 4 8 10 12 14 6 V DS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C DD [ fF ] f T [ GHz ] 160 2.0 V DS = 14V V GS = 5V 120 1.5 80 V GS = 9V 1.0 V DS = 5V 40 0.5 V DS = 1V 0 0 0 2 4 8 10 12 14 0 3 9 12 6 6 V DS [ V ] V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C DG [ fF ] 200 160 120 V DS = 5V 80 V DS = 1V V DS = 0V 40 0 - 6 - 3 0 6 9 12 3 V GS [ V ]

MOS Model 20: experimental data µ m, T = 25 o C 14V SOI-LDMOS: T ox = 60 nm, W = 50 µ µ µ µ m, L = 5 µ µ µ C DG [ fF ] diffused doping 200 in channel region 160 120 V DS = 5V 80 V DS = 1V V DS = 0V 40 0 - 6 - 3 0 6 9 12 3 V GS [ V ]

outline • introduction • MOS Model 20 – DC-model • comparison with experimental data – nodal charge model • quasi-saturation • summary

quasi-saturation gate B/S D LOCOS High-voltage n+ n+ n - drift region p+ p-well buried oxide (box) saturation may occur in drift region

quasi-saturation MM 20 G B/S D new MM 20: includes quasi-saturation

quasi-saturation G D B S n+ n+ p+ Di p n-