Interface to the DAQ and Modifications to the WIBs/PTCs Marco - - PowerPoint PPT Presentation

Interface to the DAQ and Modifications to the WIBs/PTCs

Marco Verzocchi - Fermilab Cold Electronics Workshop – Brookhaven National Laboratory 17 July 2018

Content

• ASICs Timeline
• Submission of “new” cold ADC and COLDATA
• Timeline for next generation(s) prototypes
• Test Plans
• Standalone and system tests of new ASIC(s)/FEMBs
• Different setups
• Evolution past Spring 2019

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Interface with the DAQ (i)

• All the trigger functionality (i.e. analyse the data streams to

extract information that is used to build the trigger, buffer locally the data for ~30s while waiting for a supernova trigger, zero suppression, noise filtering) is implemented in the DAQ backend

• The FPGA in the WIB will only be responsible for merging data

streams (if necessary) and for minimal data monitoring

• Ensure data integrity, monitor / mask missing channels
• In case of problems the WIB FPGA will insert flags in the data

stream, but not issue requests for re-synchronization / stop the DAQ, this should be done by the DAQ

• Allows for use of cheaper FPGAs in the WIB and simplifies the

design

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Interface with the DAQ (ii)

• Hardware: the fibres connecting the WIBs to the DAQ backend

in the central utility cavern (CUC)

• The fibres themselves could be moved from DAQ to CE if this helps

balancing the CORE costs. Routing of the fibres to be done by Technical Coordination. Connection on the cryostat side is our responsibility, on the CUC side it’s DAQ responsibility

• The DAQ backend is an item of debate within the DAQ group
• We do not care (as long as it works)
• What we really need to agree on is the design of the fibre plant

and the link speed

• At the collaboration meeting we agreed to remove the lowest speed
• ption from consideration
• Link speeds between 2.5 Gbit/s and 10 Gbit/s only are still

considered

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Fibre Plant (various options)

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Impact of link speeds

• As soon as we agree to transmit data faster than the speed of

the link from the FEMB to the WIB the FPGA inside the WIB needs to merge the data streams from multiple links from the FEMB

• This plus some very basic data monitoring is all the functionality that

is foreseen for the WIB

• Fewer links:
• More aggressive merging in the FPGA, less fibres
• Make sure that the backend can deal with the data coming on a

single fibre and that there is no need for deserializing the data on the backend

• 5 Gbit/s and 10 Gbit/s are the preferred options
• Matt will present results of data transmission at 10 Gbit/s in the next

presentation

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Links and fibres

• The current interface document (I have an updated draft that

needs to be circulated) describes at length the requirements on the fibre plant:

• Expected fibre length ~300m
• Multimode fibres, trying to use OM3 (cheaper) quality fibres
• Only 1 patch panel, preferably inside the CUC
• Bundles of 12 or 24 fibres
• This means 1 bundle of 24 fibres at 10 Gbit/s or 4 bundles of 12 fibres at

5 Gbit/s for each cryostat penetration (2 APAs)

• The vendor will provide us with fibre bundles that have an MTP

connector on the CUC side (where the patch panel is) and single fibre connectors on the WIB side

• Order all identical bundles, accommodate the slack in the cable trays on

top of the cryostat

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Data Format

• We will need a preliminary data format for the TDR, this will be

an evolution of the protoDUNE data format describe in DocDB 1701

• Do we decode the data inside the WIB and than pack it again ? In

this case the data format could be common for COLDATA/CRYO based solutions (different 8b/10b and 12b/14b encoding), otherwise need to plan for 2 possible data formats until we do the ASIC selection

• DAQ group will write data unpacker (need fast version to be

used inside the backend)

• Try to avoid multiple version, CE will need to check that data

unpacked properly

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Clock Distribution (i)

• We will use a system identical to the one in use at protoDUNE
• Clock, synchronization and trigger signals distributed over serial

data link

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Clock Distribution (ii)

• Difference will be change of clock from 50 MHz to 64 MHz (or

56 MHz)

• Some other consortium that has not yet designed their electronics

will for sure complain

• Mix of active electrical fan-outs and passive optical fan-outs
• Distribute to high number of “end points” at low cost
• Hardware at “end point” simple:
• minimum: clock and data recovery (CDR) chip
• Clock recovered from the data stream
• Signals decoded by firmware in FPGA.

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Other aspects of DAQ interface

• We need to specify clearly how the ASICs on the FEMB are

synchronized, what happens upon resets

• This is not yet written down in the interface document
• What happens during calibrations
• There is some sort of grey area between DAQ, Software and

Computing, CISC, and the consortia (mainly Cold Electronics) that needs to be clarified

• Will have a meeting on this next week

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WIB and PTC

• In principle try to keep the changes to a small number when

moving from protoDUNE to DUNE (will depend on ASIC choice)

• Revisit power distribution (fewer voltages)
• Change (if needed) fibre connection
• Do we want to add an RTD on the WIBs which is connected to

the detector safety system (interlock) [but not connected electrically to the WIB itself) ? Would it be better to put this RTD inside the chimney and connect it to the outside world like the

• ther RTDs that belong to the CISC ?

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