Integrating Dynamic Thermal Via Planning With 3D Floorplanning - - PowerPoint PPT Presentation
Integrating Dynamic Thermal Via Planning With 3D Floorplanning Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian EDA Lab, CS Dept, Tsinghua University Hannah Yang, Vijay Pitchumani, Strategic CAD lab, Intel Corporation Chung-Kuan
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian EDA Lab, CS Dept, Tsinghua University Hannah Yang, Vijay Pitchumani, Strategic CAD lab, Intel Corporation Chung-Kuan Cheng, CSE Dept, UCSD Thursday, April 13, 2006
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Thermal Model
Heuristic Method & Divide-
and-
conquer Method
Our Contribution
Analytical solution for detailed thermal via distribution
Integrating thermal via planning into 3D floorplanning
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Improved global Interconnect Interconnect performance performance
Reduce footprint footprint / Improve packing density / Improve packing density
“Mixed Signal Mixed Signal” ” Integration Integration
Heat Dissipation
Reliability
Design Complexity
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UCLA, Prof. Jason Cong Cong’ ’s s Group Group
Thermal-
driven 3D floorplanning, ICCAD 3D floorplanning, ICCAD’ ’04 04
3D global routing with thermal via planning thermal via planning, ASP , ASP-
DAC’ ’05 05
Post-
floorplanning thermal via planning thermal via planning, ICCAD , ICCAD’ ’05 05
MEVA-
3D: Performance evaluation in 2D/3D designs, ASP-
DAC’ ’06 06
UMN, Prof. Sachin Sapatnekar Sapatnekar’ ’s s Group Group
Post-
placement thermal via planning thermal via planning, ISPD , ISPD’ ’05 05
Thermal-
driven 3D global routing, ASP 3D global routing, ASP-
DAC’ ’06 06
Gatech, , thermal thermal/power noise/congestion optimization in 3D ICs /power noise/congestion optimization in 3D ICs (ISCAS (ISCAS’ ’04, ASP 04, ASP-
DAC’ ’04 & ASP 04 & ASP-
DAC’ ’05) 05)
MIT, 3D placement & routing tool for wirelength wirelength/performance and /performance and thermal thermal optimization
(ASP (ASP-
DAC’ ’03 & ISPD 03 & ISPD’ ’04) 04)
U Wisconsin, Chip-
level 3D Thermal Analysis Thermal Analysis Tool Tool (ISPD (ISPD’ ’03) 03)
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Resistive Thermal Model (CFD Research Corporation)
The 3D circuit stack is divided by a two-
dimensional array of tile
stacked tiles,
These tile stacks are connected by lateral thermal resistances. Within Within each tile stack, a thermal resistor is modeled for each device l each tile stack, a thermal resistor is modeled for each device layer. ayer.
Through solving the linear system RT = P RT = P, the temperature on each , the temperature on each node could be determined. node could be determined.
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Inter-layer Layer 4 Layer 3 Layer 2 Layer 1 Substrate Inter-layer Inter-layer Q Q Q Q
Thermal via number is in proportional to the heat flow inside that tile heat flow inside that tile
Thermal via number in the figure is
Thermal Vias
Lowering the thermal resistance between different layers different layers
Thermal resistance:
via layer e
R R R 1 1 1 + =
Heuristic Method for T-
Via Planning
k j k j
I I n n : : =
I4=Q I3=2Q I2=3Q I1=4Q
3 : 2 : 1 : :
2 3 4
= n n n
T-
Via number should be minimized and they are placed to hot areas to make the greatest impact. placed to hot areas to make the greatest impact.
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Heuristic Method (ASP-
DAC’ ’05 & ISPD 05 & ISPD’ ’05) 05)
Divide-
and-
conquer Method (ICCAD’ ’05) 05)
Given initial floorplanning results, determine vertical and horizontal izontal thermal via distribution sequentially; thermal via distribution sequentially;
Vertical thermal via distribution: analytical solution;
Horizontal thermal via distribution with heuristic method heuristic method. .
Implemented in a multi-
level global routing framework.
Drawbacks: (i) The heuristic method cannot generate optimal T-
Via planning; (ii) It is too time consuming to be integrated into planning; (ii) It is too time consuming to be integrated into floorplanning floorplanning
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Analytical solution for thermal via planning
Heuristic method:
Divide-
and-
conquer method:
Our solution
j i j i
I I n n : : =
j i j i
I I n n : : =
j i j i j i j i
I I n n Horizontal I I n n Vertical : : : : : : = =
Integrate thermal via planning into hierarchical 3D floorplanning floorplanning
Inter-
layer partition problem to minimize total number of thermal vias vias are formulated and solved. are formulated and solved.
Fast white space redistribution to generate floorplans floorplans feasible for feasible for thermal via insertion. thermal via insertion.
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Temperature rise on the i i-
th layer
amb i l k l j j l k j j b i
T P R P R T + + =
= = = 2 1
) (
s l K R × = α
layer i via i
K m K m K ) 1 ( − + =
Thermal conductivity calculation
The relationship between R R and and K K
) ( ) (
i i
m F R F T = =
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Temperature-
constrained vertical thermal via planning problem:
layer layer via amb k j j b k i k i j j i layer k i i
K K K T T P R P m R t s m − = ≤ + + +
= = = =
λ λ
1 2 2
) 1 ( . . min
∑ ∑ ∑ ∑
= = = =
− − = ∆ + − ∆ + =
k j j b amb k i k i j j i layer k i i
P R T T T where P m R T m f
1 2 2
) ) 1 ( ( λ µ k i m f
i
≤ ≤ = ∂ ∂ 2 , /
The convex programming problem could be solved directly by KKT KKT
, / ) 1 (
1 2 2 2
λ − − − =
∑
=
I R T T I I R m
b amb k i i layer
k i I I m m
i i i i
≤ ≤ = + +
− −
2 , : 1 : 1
1 1
λ λ
∑
=
=
k i l l i
P I where
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Optimal V-
TV Distribution: Desired temperature rise on each layer
Vertical heat flow in a grid is the sum of heat flow from all other grids ther grids
=
i ijk jk
H I
amb i l k l j j l k j j b i
T P R P R T + + =
= = = 2 ' 1
) (
Desired thermal gradient for each tile
ik ik i i i
R I T T T = ∆ = −
−1
Heat Flow Analysis
Ii,k+1 Pi,k Hi,j Ij,k+1 Pj,k Ii,k Ij,k
+
+ =
l il ij i k ki ijk
R R I P H 1 / 1 ) (
, 1
ij h i ij
l R R R + =
Heat flow from a grid to other gird is inversely proportional to the thermal resistance of the proportional to the thermal resistance of the flow path. flow path.
I is related to is related to R R so it should be updated frequently. so it should be updated frequently.
) (
ik
R f = ) (
ik
m g = ) (
ik
m f =
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Temperature-
constrained horizontal thermal via planning problem:
N k T R R I P R I R t s m min
i N j N l ijl ijk j i ij ik ik ik N k ik
, , 1 / 1 / 1 ) ( . .
1 1 , 1 1
K = ∆ ≤ + × = ×
∑ ∑ ∑
= = + =
N s k l I P l I P m m
N j js j i ij N j jk j i ij is ik
≤ ≤ + + =
= + = +
, 1 , : :
1 , 1 1 , 1
i N k N j ik jk h j i ij i N k ik
T N R l R I P R t s m min ∆ ≤ + +
∑ ∑ ∑
= = + = 1 1 , 1 1
/ 1 1 . .
is ik is ik
I I m m : : =
Simplified convex programming problem formulation:
Nearly optimal solution for CP:
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Hierarchical 3D Floorplanning
Partition blocks into different layers
Generate floorplans for all these layers
This 3D floorplanning flow has been implemented for wirelength optimization implemented for wirelength optimization (ISCAS (ISCAS’ ’05) and thermal optimization 05) and thermal optimization (TODAES (TODAES’ ’06). 06).
Smaller solution space
More stable for thermal optimization
Key Problem:
Formulate and solve the inter-
layer partitioning problem for thermal via planning. planning.
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Problem Formulation:
k i k A A const P t s m
i k i i k i i
≤ ≤ ≤ ≤ =
∑ ∑
= =
1 , | / | 1 . . min
1 2
β β
k i k A A const P t s P
i k i i k l k l i i
≤ ≤ ≤ ≤ =
∑ ∑ ∑
= = =
1 , | / | 1 . . min
1 2
β β
k const R T T P R m
b amb k i k i l l layer k i i
− × − − =
∑ ∑ ∑
= = =
) ( ) (
2 2 2
λ
β β ≤ ≤ | / | 1 . . max
1 1
k A A t s P
k i k A A const P const P t s const P P P
i k i i k l k l i i k i i k l k l i i
≤ ≤ ≤ ≤ = − = + = +
∑ ∑ ∑ ∑ ∑ ∑
= = = = = =
2 , | / | 1 ' . . ' min
* 1 2 3 2 3
β β
Solving knapsack problem: determine P1
Solution Method:
The inter-
layer partitioning problem could be solved through solving a sequence of knapsack sub sequence of knapsack sub-
problems.
β β ≤ ≤ | / | 1 . . max
2 2
k A A t s P
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Inter-
layer partitioning: determine desired temperature on each layer.
Floorplanning using SA engine based on CBL representation
Cost function:
Thermal resistances are updated after horizontal thermal via planning anning and the maximal temperature is calculated by solving linear equa and the maximal temperature is calculated by solving linear equations. tions.
) (
max 2 1
T T w W w A − + + = Ψ
Thermal vias should be arranged in the white space between blocks. s.
White space resources may be not enough for thermal via insertion not enough for thermal via insertion in hot area. in hot area.
A fast and simple white space redistribution method is proposed to deal to deal with it during with it during floorplanning floorplanning process. process.
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Compare our algorithm with UCLA’ ’s algorithm in ICCAD s algorithm in ICCAD’ ’05 05
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Mathematical modeling and analytical solution for minimizing thermal via rmal via number with maximal temperature constraint. number with maximal temperature constraint.
Optimal vertical thermal via distribution.
Nearly optimal horizontal thermal via distribution.
Thermal via planning is integrated into 3D floorplanning process with our with our two two-
stage approach.
Inter-
layer partitioning problem is formulated and solved for thermal via via number minimization. number minimization.
Fast white space redistribution method is proposed for thermal via via insertion during floorplanning. insertion during floorplanning.