[PDF] - Incremental Physical Design Jason Cong UCLA Majid Sarrafzadeh PDF Document

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Incremental Physical Design

Jason Cong UCLA Majid Sarrafzadeh Northwestern

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Outline

PART I: Introduction & Motivation PART II: Partitioning, Floorplanning, and Placemenet PART III: Routing PART IV: Conclusion

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PART I: Introduction & Motivation

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Introduction & Motivation

Concurrent optimization:
problems are getting complex
need quick evaluation of a number of alternatives

Existing algorithms are “incremental”

what can we say about the quality of the final solution? when to do, and how much, incremental “moves”?

A more fundamental concept: Given a solution, assess

its quality

Design for change The right data structures

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Current Methods

Ad-hoc (low-temp annealing or rip-up and reroute) No or very little understanding of the solution quality Painful and slow updates May have undesired global impact There has been very little done on the topic (We provide a reasonable list of references as a starting

points: data structures, layout algorithms, synthesis algorithms, etc)

Today’s presentation is meant to serve as a motivator

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PART II: Partitioning, Floorplanning, and Placement

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Partitioning

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Incremental Partitioning

An original (hyper)graph and its near-optimal partitioning

results are given.

An incrementally changed (hyper)graph is obtained by

adding/deleting vertices/edges from the original graph.

Incremental partitioning problem is to find the near-

ptimal partitioning for the changed (hyper)graph

without doing from the scratch.

Incremental partitioning should be much faster than the

riginal partitioning.

It is preferable to use the existing partitioning results for

the original (hyper)graph.

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Original Graph

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One Vertex Changed (e.g., resized)

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One Edge Added (logic restructuring)

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3rd Vertex Changed

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0-proximity Vertices

0-proximity 0-proximity 0-proximity 0-proximity 0-proximity

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1-proximity Vertices

0-proximity 0-proximity 0-proximity 1-proximity 1-proximity 0-proximity 0-proximity 1-proximity

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2-proximity Vertices

0-proximity 0-proximity 0-proximity 1-proximity 1-proximity 0-proximity 2-proximity 1-proximity 0-proximity

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Partitioning Problem on the Original Graph

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Partitioning Problem on the Changed Graph (inf-threshold)

0-proximity 0-proximity 0-proximity 1-proximity Changed Vertices 0-proximity

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0-Threshold Incremental Partitioning

0-proximity 0-proximity 0-proximity 0-proximity 0-proximity

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1-Threshold Incremental Partitioning

0-proximity 0-proximity 0-proximity 1-proximity 1-proximity 0-proximity 0-proximity

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Incremental Partitioning with 1% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Net-cut results normalized to infinity-threshold results.

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Incremental Partitioning with 1% Change In the Original Graph

0.2 0.4 0.6 0.8 1 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Runtime normalized to infinity-threshold results.

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Incremental Partitioning with 5% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 1.4 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Net-cut results normalized to infinity-threshold results.

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Incremental Partitioning with 5% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Runtime normalized to infinity-threshold results.

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Incremental Partitioning with 10% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Net-cut results normalized to infinity-threshold results.

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Incremental Partitioning with 10% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Runtime normalized to infinity-threshold results.

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Incremental Partitioning with 20% Change In the Original Graph

0.5 1 1.5 2 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Net-cut results normalized to infinity-threshold results.

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Incremental Partitioning with 20% Change In the Original Graph

0.2 0.4 0.6 0.8 1 1.2 ibm01 ibm02 ibm03 ibm04 ibm05 0-threshold 1-threshold 2-threshold inf-threshold

Runtime normalized to infinity-threshold results.

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Incremental Partitioning with 1% Change In the Original Graph

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Incremental Partitioning with 5% Change In the Original Graph

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Incremental Partitioning with 10% Change In the Original Graph

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Incremental Partitioning with 20% Change In the Original Graph

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Some more ideas

Localized proximity Net-list dependent proximity New/ targeted algorithms (not “locked full partitioner”)

for incremental partitioning

Create an initial solution that is suitable for change

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Floorplanning

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Incremental Floorplanning

Do not resize the floorplan if not needed or if not needed

“badly” (based on an enhanced sizing tree) [Crenshaw- Sarrafzadeh]

Time Ratio Plot

1 10 100 1000 10000 Vec1x Vec5x Vec10x Vec50x Vec100x Vector File Ex10 Ex20 Ex50

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A slack based sizing tree (for quick decision making)

w+ - slack in width h+ - slack in height Horizontal critical path Vertical critical path

6 1 2 3 4 5

7 5 6 10 5 4 5 5 5 8 7 8 10 11 14 7 7 8-7

2 1 6 5 3

w+=0 h+= 2 w+=0 h+= 0 w+=0 h+= 0 w+=3 h+= 0 w+=0 h+= 2 w+=0 h+= 0 w+=0 h+= 0

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w+=0 h+= 0 w+=0 h+= 0 w+= 1 h+= 0 w+=2 h+= 0

10-8

TSS

module width height 1 3 2 2 2 3 4 4 3 5 2 6

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Speed-up after a series of moves

(adding buffers, sizing, gate duplication

User Times for Finding Area Improving Moves

0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 900.00 f r a c t

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f r a c t

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f r a c t

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f r a c t

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s t r u c t

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s t r u c t

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s t r u c t

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2 s t r u c t

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3 s t r u c t

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5 p r i m a r y 1

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p r i m a r y 1

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p r i m a r y 1

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p r i m a r y 1

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2 p r i m a r y 2

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5 benchmarks CPU runtime (s) slack-aware greedy-local greedy-global

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(Floorplan) Design for Change

Accurate data is not available in early phases:
Missing cells: Some cells have not been designed yet. Use

estimates from previous design.

Formulate designer’s experience in estimation of the cell area.

Evolving (cell / IP) library: Final area of modules can be estimated

from current area.

Geometric synthesis, timing improvement, ….
Nostradamus: A Floorplanner of Uncertain Designs [Bazargan-

Kim-Sarrafzadeh]

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Problem Formulation

Distribution lists for width/height:
Wi = { (wi1,p(wi1)),…,(wi,mi,p(wi,mi)) }

Σj p(wij) = 1

Hi = { (hi1,p(hi1)), … , (hi,ni,p(hi,ni)) }

Σj p(hij) = 1

Example:

W1 = { (5,0.3) , (7,0.5), (8,0.2) } W2 = { (2,0.9), (3,0.1) } H1 = { (1,.1),(2,.2),(7,.7) } H2 = { (4,.4),(6,.6) }

We could also use:
Li = { (wi1, hi1, pi1), … , (wim, him, pim) }

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Output Distributions

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Input/Output Correlation

Width: Input and output std dev of diff data sets

20 40 60 80 100 120 140

a1 a3 b1 b3 c1 c3 c5 d1 d3 e1 e3 f1 f3 g1 h1 h3 c6f1

data sets stddev Ouput deviation Scaled input deviation

Height: Input and output std dev of diff data sets

10 20 30 40 50 60 70 80

a1 a3 b1 b3 c1 c3 c5 d1 d3 e1 e3 f1 f3 g1 h1 h3 c6f1

data sets stddev Output deviation Scaled input deviation

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Experimental Results

Ratio of actual area of traditional methods to area of Nostradamus : 30% uncertainty 0% 20% 40% 60% 80% 100% 120% 140% a1 a2 a3 a4 b1 b2 b3 b4 f1 f2 f3 f4 g1 g2

Conservative Optimistic

Exp. Val.

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Experimental Results

Ratio of actual area of traditional methods to area of Nostradamus : 10% uncertainty 0% 20% 40% 60% 80% 100% 120% 140% a1 a2 a3 a4 b1 b2 b3 b4 f1 f2 f3 f4 g1 g2

Conservative Optimistic

Exp. Val.

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Placement

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Placement Problem

Input:

A set of cells and their complete information (a cell library).
Connectivity information between cells (netlist information).

Output:

A set of locations on the chip: one location for each cell.

Goal:

Total chip area and wirelength, under timing constraints.

Challenge:

Rapid growing circuit size (> 1 million).
Multi objectives (timing constraint, routability)

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Placement Problem

Input: Cells and Interconnections Output: Locations on a 2-D plane

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Predictors based on the given algorithm or based on absolute truth

A bad placement A good placement

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Placement Algorithms (both incremental, so do

we understand incremental?) Constructive Placement

e.g. Analytical optimization Build up placement from scratch. Fast, but most of them lack of solution quality.

Iterative Improvement

e.g. Simulated annealing Gradually improve existing solutions. Slow, but with good solution quality, easy to consider multi-objectives.

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Incremental Placement

Caused by:

Adding cells/nets Meeting timing constraints

while minimizing total chip area.

Reducing congestion

A post processing algorithm is more effective

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Proximity In Placement

Topological Proximity Geometrical Proximity

A B C B A

Cell A and B are topological proximate Cell A and B are geometrical proximate

In a good placement, topological proximity and geometrical proximity generally correlate well

C D

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Preliminary studies

Reducing length of long net Helps meeting timing constraints

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Shrinking long nets

Pick up cells which are located on the edge of the Bounding box, switch them with other cells.

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Experimental setup

Given a placement produced by a fresh placement run, find the longest nets, Let its length be L, then find all the nets which are longer than (1-x%)L, reduce all these long nets to (1-x%)L or less. Data reported are number of long nets and x%

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Experiment results

It is not difficult to reduce the longest net by up to 20% without considerably increasing the total wirelength

N/A 13 1.85% 10 0.14% 2 0.06% 1 25114

avql

1.67% 6 0.78% 5 0.16% 3 0.03% 1 21854

avqs

N/A 5 0.06% 1 0.04% 1 0.01% 1 15059

industry3

N/A 39 N/A 17 0.48% 6 0.06% 2 12142

industry2

N/A 13 2.48% 7 0.37% 3 0.06% 1 2907

Primary2

WL

# nets

WL

# nets

WL

# nets

WL

# nets

30% 20% 10% 5 %

Length of long nets are reduced to (1-x)% of longest net

#cells Circuit

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Experiment results

Experiments of Shrinking Long Nets

0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 3.50% 0% 5% 10% 15% 20% Long nets length reduction Total WL increase primary2 industry2 industry3 avqs avql

It’s a greedy, simple approach. More effective algorithms are to be studied.

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PART III: Incremental Routing

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Incremental Routing Problem

Basic operations:

Net removal (easy) Net addition (focus of this talk)

Objective

Preserve as much previous results as possible

Applications

Changes of the netlist due to functionality modification Modification of placement due to performance consideration Change of a route (width, spacing, possible buffer insertion)

after post-layout extraction and simulation

...

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Sub-problems in Incremental Routing

Single Net Routing

No change of existing routes

Rip-up and Reroute

Change some existing routes but no change of

placement/floorplan

Incremental Floorplan and Placement Update

Invoke when Rip-up & re-route fails

Increasing flexibility Increasing runtime

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Single Net Routing Problem

Problem Formulation

Given

a set of existing routes/obstacles
the width and spacing of a given net

Find a valid route for this net

Need for gridless (GLS) routing

Variable wire width for delay optimization Variable wire spacing for noise constraints

Challenges

Construction of GLS routing graph Representation of GLS routing graph Search on GLS routing graph

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Existing Approaches to GLS SNR

Obstacle expansion

Reduced to zero-width routing

Construction of routing graph

Tile-based approach Point-based approach

Uniform grid graph Non-uniform grid graph

Search on the routing graph

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Obstacle Expansion for Gridless Routing

Expansion of Obstacles According to Width Rule and

Spacing Rule to Reduce the Routing Problem into Zero Width Routing Ww=4 Sw=2 Ew=Ww/2+Sw

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Tile-based Approach

[Margarino CAD’87; Sechen ISPD’98]

1. Tile Partition
2. Corner-Stitching

Data Structure

[Ousterhout, TCAD84]

3. A Tile-to-Tile

Searching s t

T1 T2 T4 T3 T7 T5 T6

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Uniform Grid Approach [Lee’61]

Representing the region using uniform grids Graph can be very large!

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Minimal Routing Graph Approach

[Wu T-Comp’87; Zheng TCAD’96]

Extend the boundries

f expanded rectangles

Sparser than uniform- grid but irregular

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Limitations of Existing Approaches for Incremental Routing

Pre-expansion of obstacles - very costly

Need to re-expand if routing a net of different width and/or spacing

Pre-construction of routing graph - very costly

Incremental route may use only a small portion of the graph (but

cannot be determined a priori)

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S T

Non-Uniform Grid Graph Approach

[Cong-Fang-Khoo, ICCAD’99]

Given a set of obstacles and a source s and sink t
GS is an orthogonal grid graph

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S T

Implicit Representation of GS

y1 y2 y3 y4 y5 y6 y7 y8 x1 x3 x4 x2 x5 x6 x7 x8 x9 x10

Store x, y locations in arrays
Space Pre-construction
Can be maintained incrementally (O(logN) time)

) (N O

) log ( N N O

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S T

Searching on GS

y1 y2 y3 y4 y5 y6 y7 y8 x1 x3 x4 x2 x5 x6 x7 x8 x9 x10

Determine the Location of Neighboring Node: Easy

Free?

Determine If the Location Is Valid: Difficult

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No Pre-Expansion of Obstacles

Point enclosure query -> rectangle intersection query

a b d c q a b d c q

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Our 2-D Query Data Structure

a b d c q Data Structure

Is q in free space

Query

c b,d

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Experimental Results

701172 25668 2 3

2741.5 x 3192.8

Eco-7 372240 13959 2 3

2926.1 x 1676.8

Eco-6 196947 7542 2 3

1556.6 x 1676.8

Eco-5 232633 6417 2 3

1372.5 x 1608.6

Eco-4 232004 6417 5 3

1372.5 x 1593.3

Eco-3 232453 6417 2 3

1372.5 x 1593.3

Eco-2 232309 6417 3 3

1372.5 x 1593.3

Eco-1 Rects Cells Pins Layers Dimension Ex.

Examples Comparison

Explicit Uniform Grid Graph Iroute from Magic Layout Editor [Arnold 88]

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Comparison of Memory Usage

Unit: MB

3.0 1.00 14.3 Ratio 84.7 43.6 641.1 Eco-7 52.6 15.9 359.4 Eco-6 35.2 12.7 191.0 Eco-5 32.6 10.9 161.7 Eco-4 32.6 7.2 160.2 Eco-3 32.7 10.9 160.2 Eco-2 32.7 10.9 160.2 Eco-1 Iroute Non-Uni. Grid

Uni. Grids

Ex.

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Comparison of Runtime and ECO Routing Quality

47591 / 20 79.79 35690 / 74 38.2 Eco-7 56423 / 20 74.29 37858 / 70 24.7 Eco-6 34543 / 12 43.14 27061 / 54 12.3 Eco-5 24385 / 153 57.39 21760 / 122 24.0 Eco-4 36593 / 103 68.70 34736 / 110 34.5 Eco-3 13162 / 62 26.58 11332 / 44 6.3 Eco-2 22629 / 89 42.15 17374 / 66 19.1 Eco-1 Iroute Result(wl/vc) Time(s) Non-Uniform Result(wl/vc) Time(s) Ex.

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Sub-problems in Incremental Routing

Single Net Routing

No change of existing routes

Rip-up and Reroute

Change some existing routes but no change of

placement/floorplan

Incremental Floorplan and Placement Update

Invoke when Rip-up & re-route fails

Increasing flexibility Increasing runtime

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Rip-up and Reroute

Invoke when net-by-net routing fails Objectives

Complete all the nets Minimize number of rip-ups

Challenges

Gridless nature of routing problem makes routing resource

difficult to model and manage

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Overview of Existing R&R Approaches

Maintain Design-Rule Correctness

Pros: always has a valid partial solution Cons: too restrictive; net order dependent

Allow Temporary Design-Rule Violation

Pros: allow cross and touch [Kawamura ICCAD’90], more flexibility Cons:

Difficult to model routing resources in gridless routing Lack of global picture

Planning Based Ripup and Re-route

Preferred approach

Can model routing resources with flexible resolution Allow a more global view Can be applied iteratively

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Planning Graph Construction

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Planning Based Rip-up & Re-route

Advantages

More Global Picture Reasonably Accurate Routing Region Information

Very efficient on the planning graph Similar to global routing, but only serve as a guide Re-planning Approaches

Local Refinement Ripup and Re-plan

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Local Refinement

S1 S2 S3 T1 T2 T3

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Local Refinement

S1 S2 S3 T1 T2 T3

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Local Refinement

S1 S2 S3 T1 T2 T3

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Ripup & Re-planning

S1 S2 S3 T1 T2 T3

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Sub-problems in Incremental Routing

Single Net Routing

No change of existing routes

Rip-up and Reroute

Change some existing routes but no change of

placement/floorplan

Incremental Floorplan and Placement Update

Invoke when Rip-up & re-route fails

Increasing flexibility Increasing runtime

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Incremental Floorplan and Placement Update

Problem Formulation

When rip-up and re-route fails, determine how to complete the

design with minimum changes of the floorplan and/or placement

Need efficient heuristics to decide what routing regions

to enlarge

May apply compaction/de-compaction techniques Earlier discussions on incremental floorplan and

placement also apply

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Conclusions

Design iteration is unavoidable Incremental PD is an important enabling technology to

allow design convergence

Trade-off of efficiency, preservability, and design quality

is the key issue in incremental designs

Much work is needed in this area Need to start thinking about “Design for Incremental

Changes” (DFI)

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Acknowledgements

NSF, DARPA, and Fujitsu Laboratories Jie Fang and Kei-Yong Khoo from UCLA Kiarash Barzagan, Maogang Wang, and Xiaojian Yang