Increa easing sing the Accur urac acy y of Inter erconn - - PowerPoint PPT Presentation
The World Leader in High Performance Signal Processing Solutions TAU W Workshop op 2014 Increa easing sing the Accur urac acy y of Inter erconn connect ct Derates: tes: A Path Based ed Meth thod od Ryan Kinnerk, Dr. Emanuel
The World Leader in High Performance Signal Processing Solutions
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Sources of interconnect variation Impact of interconnect variation Standard interconnect variation margining methodologies Proposed interconnect variation margining methodology Future work and conclusions
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Lithography Optical Proximity Correction Position in the optical field Lens aberrations Mask imperfections Planarization Chemical Mechanical Planarization Deposition/Etch Environmental factors Misalignment between lithographic steps Different equipment used on adjacent metal layers Temperature & pressure
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Comparison of interconnect delays in timing environments
Note that SI analysis was disabled
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Statistical STA Associated problems: i.
ii.
iii.
iv.
v.
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Using vendor provided timing margin recommendations These vary from vendor to vendor but are likely to look similar to
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Applying the example timing recommendations
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Associated problems: i.
ii.
iii.
iv.
v.
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Consider the ways in which varying interconnect RC affects non-SI
i.
ii.
iii.
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SI analysis is disabled Initially, STA is run as before using vendor recommended timing
The proposed methodology is then applied to paths with little or no
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Assume for illustration purposes that… i.
ii.
iii.
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STA is rerun on each corner with no interconnect derates applied Instead of derates, the most pessimistic parasitic corner is used for
Most pessimistic parasitic corner determined using: (DNET + DCELL-UP + DCELL-DOWN) Let…
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Assume a hold check on the Best parasitic corner All launch and data path interconnects should be modelled as early If DALL-WORST < DALL-BEST on any interconnect along either the
WORST) in each instance
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Similarly, all capture path interconnects should be modelled as late If DALL-WORST > DALL-BEST on any interconnect along the capture
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How is DNET measured?
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How are DCELL-UP/DCELL-DOWN measured?
UP/DCELL-DOWN across parasitic corners using lumped RC
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A real example of the differences in resultant slack between the
The 100 most critical hold and setup paths were considered
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Include additional designs Include additional 65nm CMOS process Compare slacks using various methods to slacks from using Monte
Expand methodology to account for the effects of SI Account for the susceptibility paths to interconnect variation Account for the number of paths with little or no slack
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Standard interconnect variation margining methodologies are
The proposed methodology represents a reasonable trade-off
How path delays are affected by interconnect variation is modelled A more accurate and robust analysis with respect to using vendor
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Dr. Emanuel Popovici Colm O’Doherty Alan Whooley Seamus Power