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Impact of Custom Interconnect Masks on Cost and Performance of Structured ASICs Final Doctoral Exam Usman Ahmed Department of Electrical and Computer Engineering April, 2011 Overview Motivation Research Problem Previous Work

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Impact of Custom Interconnect Masks on Cost and Performance of Structured ASICs

Final Doctoral Exam Usman Ahmed

Department of Electrical and Computer Engineering

April, 2011

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2

Overview

  • Motivation
  • Research Problem
  • Previous Work
  • Contributions

– Cost Model to Estimate Structured ASIC Die-cost – Structured ASIC Evaluation Framework – Area, delay, power, and die-cost trends for Structured ASICs

  • Limitations and Future work
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3

Motivation

IP Blocks (e.g., memories, multipliers, microprocessors) I/O Cores Logic Fabric

All mask layers are customized for a design

  • Most layers are prefabricated, shared by all designs

User design obtained by customizing only a few interconnect layers

  • All mask layers are prefabricated, shared by all designs

User design obtained by programming memory cells

  • Interconnect

Layers Transistor Layers

Crosssection

Masks are Used to Fabricate Each Layer

Masks are used to fabricate each layer

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4

Motivation

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Research Problem

How is the cost and performance of Structured ASICs affected by the number of custom masks?

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Types of Structured ASICs

  • Which masks need to be customized?

Interconnect Layers Transistors

Via Programmable (VPSA) Metal-and-via Programmable (MPSA)

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Types of Structured ASICs

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8

Previous Work

  • Academic Efforts

– Ran & Sadowska: VPSA logic and interconnect fabrics – Pillegi et al. and Koorapaty et al.: VPSA logic block – Kheterpal et al.: VPSA interconnect fabrics – Veredas et al.: MPSA (Zelix) – Nakamura et al.: VPSA (VPEX) – Chau et al.: VPSA logic block

  • Point solutions

– Logic block and routing fabrics with fixed configurability

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Previous Work

VPSA VPSA MPSA MPSA MPSA MPSA MPSA MPSA MPSA MPSA MPSA

  • Commercial Efforts

– Point Solutions – Mostly MPSAs – Wide range for configurability – Products with high configurability have been discontinued

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Contributions

  • 1. Cost Model to Estimate Die-cost of

Structured ASICs

  • 2. Structured ASIC Evaluation Framework
  • 3. Area, Delay, Power, and Die-cost Trends

for Structured ASICs

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11

Contributions

  • 1. Cost Model to Estimate Die-cost of

Structured ASICs

  • 2. Structured ASIC Evaluation Framework
  • 3. Area, Delay, Power, and Die-cost Trends

for Structured ASICs

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Structured ASIC Die-Cost

  • Primary cost components

– Die Area – Number of configurable layers (New for structured ASICs)

  • Metal layers used for routing
  • Configured by one or more via, or metal-and-via masks
  • Secondary cost components

– Die Yield – Mask-set and processing costs – Volume requirements

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Cost Model

  • Variables

– Die Area and Yield – Configurable layers

  • Constants

– Mask/wafer processing cost – Volume requirements – Architecture Related

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Cost Model

  • At constant cost, area can be traded for number
  • f customizable layers

MPSA

Core Area (mm

2)

Slope ≈ 15mm2/Layer

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15

Contributions

  • 1. Cost Model to Estimate Die-cost of

Structured ASICs

  • 2. Structured ASIC Evaluation Framework
  • 3. Area, Delay, Power, and Die-cost Trends

for Structured ASICs

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Structured ASIC Evaluation Framework

  • Architecture Modeling

– Logic Fabric – Interconnect Fabric

  • Metrics
  • CAD Flow
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Metrics

  • Cost

– Detailed cost model (just presented)

  • Area

– Chip Area

  • Delay

– Average net delay (Elmore model)

  • Power

– Total metal + via capacitance

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CAD Overview

Input Circuit

  • #Routing Layers

Routing Grid Resolution Routing Grid Capacity No Logic Fabric Architecture Logic Elements Physical Size Pin Locations

  • Area/Delay/Power/Cost Estimate
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Contributions

  • 1. Cost Model to Estimate Die-cost of

Structured ASICs

  • 2. Structured ASIC Evaluation Framework
  • 3. Area, Delay, Power, and Die-cost Trends

for Structured ASICs

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Performance and Cost Trends

  • MPSAs

– Two Benchmark Suites

  • Homogeneous (MCNC) Circuits
  • Heterogeneous (eASIC) Circuits

– Comparison to CBIC costs – Impact of Whitespace Insertion

  • VPSAs

– Fixed-metal Routing Fabrics – Impact of Logic Block Pin Positions – Power, Delay, Area, and Die-cost – Comparison to MPSAs

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Performance and Cost Trends

  • MPSAs

– Two Benchmark Suites

  • Homogeneous (MCNC) Circuits
  • Heterogeneous (eASIC) Circuits

– Comparison to CBIC costs – Impact of Whitespace Insertion

  • VPSAs

– Fixed-metal Routing Fabrics – Impact of Logic Block Pin Positions – Power, Delay, Area, and Die-cost – Comparison to MPSAs

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Trends for Heterogeneous Circuits

  • Device Architecture

– Logic Elements

  • eCell, eDff, BlockRAM, RegFile
  • Circuits

– Up to 1 Million logic blocks

  • Placement Enhancement

– Different logic elements

  • Layout Effort
  • Dense
  • Medium
  • Sparse

Block RAM Register File Register File

eASIC Group

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  • Area and Die-Cost

23

Trends for Heterogeneous Circuits

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  • Area and Die-Cost

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Trends for Heterogeneous Circuits

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  • Area and Die-Cost

– Lowest cost obtained with 3 or 4 layers – More than 4 layers offer little advantage

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Trends for Heterogeneous Circuits

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Performance and Cost Trends

  • MPSAs

– Two Benchmark Suites

  • Homogeneous (MCNC) Circuits
  • Heterogeneous (eASIC) Circuits

– Comparison to CBIC costs – Impact of Whitespace Insertion

  • VPSAs

– Fixed-metal Routing Fabrics – Impact of Logic Block Pin Positions – Power, Delay, Area, and Die-cost – Comparison to MPSAs

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Trends for VPSAs

  • Routing Fabrics (by Ran & Sadowska)

– Crossover – Jumper20, Jumper40 – SingleVia

  • Logic Blocks

– Logic Capacity

  • 2-in,1-out to 16-in,8-out

– Layout Effort

  • Dense
  • Medium
  • Sparse

n-1 custom via layers 1 custom via layer n fixed-metal layers

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VPSA Area and Die-cost Example

  • Logic Block

– Logic Capacity: 2-in, 1-out – Layout Effort: Medium

  • MPSAs: Small Area

VPSAs: Lower Cost

  • Gap between different VPSA

Fabrics

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VPSA Area and Die-cost Trends

MPSAs vs. VPSAs VPSAs

0 to 89%

0 to 36%

1 to 10x

VPSAs are up to 50% cheaper

  • Key Observations

0 to 85% 0 to 60% 1 to 3.5x 1 to 5x

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Contributions

  • 1. Cost Model to Estimate Die-cost of

Structured ASICs

  • 2. Structured ASIC Evaluation Framework
  • 3. Area, Delay, Power, and Die-cost Trends

for Structured ASICs

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Limitations

  • Uniform Whitespace Distribution
  • No Buffer Insertion
  • No Detailed Logic Block Architectures

– “Approximate” Technology Mapping – Delay and Power of Logic Blocks – Critical Path Delay

  • Logic Block Configuration Schemes
  • Overhead of Power and Clock Networks
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Future Work

  • Short term

– Congestion-driven Whitespace Insertion – Impact of Buffer Insertion – Efficient Algorithm for VPSA Detailed Routing – Timing and/or Power Aware CAD Flows – New Logic and Interconnect Fabrics

  • Long term

– Improved Manufacturability – Ease of Design

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Publications

  • Refereed Journal Publication
  • U. Ahmed, G. Lemieux, S. Wilton, “ Performance and Cost Tradeoffs in Metal-Programmable

Structured ASICs (MPSAs),” IEEE Transactions on VLSI Systems, 2010. Available Online: http://dx.doi.org/10.1109/TVLSI.2010.2076841

  • Refereed Conference Publications
  • U. Ahmed, G. Lemieux, S. Wilton, “Area, Delay, Power and Cost Trends for Metal-

Programmable Structured ASICs (MPSAs),” International Conference on Field-Programmable Technology (ICFPT’09), Dec. 2009.

  • U. Ahmed, G. Lemieux, S. Wilton, “The Impact of Interconnect Architecture on Via-

Programmed Structured ASICs (VPSAs),” International Symposium on Field-Programmable Gate Arrays (FPGA 2010), Feb. 2010.

  • In Preparation
  • U. Ahmed, G. Lemieux, S. Wilton, “Performance and Cost Tradeoffs in Via-Programmable

Structured ASICs (VPSAs),” to be submitted to IEEE Transactions on VLSI Systems.

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Structured ASIC Vendor and User

Vendor designs and fabricates a portion of the device

  • User runs CAD tools to generate the

required data for the masks

  • Cannot make architectural decisions

Vendor prepares the necessary masks and fabricates the remaining portion of the device

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Cost Comparison

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Cost Model

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Cost Model

  • Cost of the masks for the base

(common portion) Cost of fabricating the base portion

+ +

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Cost Model

  • Cost of the masks for the base

(common portion) Cost of fabricating the base portion

+ +

Cost of the remaining masks Cost of fabricating the remaining portion

+ +

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Cost Model

  • Cost of the masks for the base

(common portion) Cost of fabricating the base portion

+ +

Cost of the remaining masks Cost of fabricating the remaining portion

+ +

Similar to Ccustom, but depends on the number of spins

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Cost Model

  • At constant cost, area can be traded for number
  • f customizable layers

MPSA VPSA

(Multiple Via Layers)

VPSA

(Single Via Layer)

Core Area (mm

2)

Slope ≈ 15mm2/Layer Slope ≈ 6mm2/Layer

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Logic Block Model

  • Characteristics of logic block

– Physical dimensions (in wire pitches) – Pin locations

  • Do not need low-level

layout details

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Parameterize Logic Block

  • Cover wide search space for logic blocks
  • Vary layout density

– Dense: Determined by # pins (small layout area) – Sparse: Determined by Standard Cell implementation

  • Vary logic capacity

– Sweep number of inputs and outputs

  • 2-input, 1-output logic blocks (shown here)
  • 16-input, 8-output logic blocks (also in paper)

– Use logic clustering (T-VPack) as tech-mapper

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Interconnect Model

  • MPSAs

– Set of equally-wide and equally-spaced horizontal or vertical wires for each configurable layer

  • VPSAs

– Detailed architecture specified for a basic tile

  • Metal segments (start, end positions)
  • Potential via sites (fixed or configurable vias)
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CAD Framework for Structured ASICs

  • Increase Placement Grid Size
  • Simulated Annealing Too Slow
  • Logic Cells Snapped to Grid
  • Can Handle different Types of

Logic Blocks

  • Detailed routing only for VPSAs
  • Difficult to find Global Routing Capacities
  • Limit the search space by performing

detailed routing only within the Global Route

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CAD Framework

  • !"#!$

%& $" '&

  • (")(

Input Circuit

  • Area/Delay/Power/Cost Estimate

#Routing Layers Routing Grid Resolution Routing Grid Capacity

  • (!)

No Yes No

!" #

Logic Fabric Architecture Logic Elements Physical Size Pin Locations Routing Fabric Architecture

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MPSA vs. VPSA Detailed Routing

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Impact of Whitespace Insertion

  • Estimated using Routing Capacity
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Impact of Whitespace Insertion

  • Area and Die-cost

Small Block Small Block

  • 60% reduction in area and 55% reduction in cost
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  • Three schemes

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Logic Block Pin Positions

  • Each pin can connect

to more tracks

  • Fewer routing tracks

in the lowest layer

  • Multiple pins per track
  • More tracks available for routing
  • Each pin can connect to fewer

tracks

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  • Three schemes

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Logic Block Pin Positions

  • Better when number
  • f routing resources is

large

  • Better when routing resources are

limited (e.g., routing layers = 2)

Experiments used best scheme for each case

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  • Significant difference between different schemes
  • Performance dependent on

– Routing fabric architecture – Number of routing layers

52

Logic Block Pin Positions

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Trends for Heterogeneous Circuits

  • Delay and Power

– Best performance obtained with 3 or 4 layers – More than 4 layers offer little advantage

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VPSA Area and Die-cost Trends

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Technology Scaling