High Resolution Digitally Trimmable Resistor
Presented by: Alek Benson, Clark Reimers, Pierce Nablo, Oluwatosin Oyenekan
High Resolution Digitally Trimmable Resistor Presented by: Alek - - PowerPoint PPT Presentation
High Resolution Digitally Trimmable Resistor Presented by: Alek Benson, Clark Reimers, Pierce Nablo, Oluwatosin Oyenekan Overview Intro Initial Research Proposed Approaches Testing Technical Difficulties Conclusion
Presented by: Alek Benson, Clark Reimers, Pierce Nablo, Oluwatosin Oyenekan
Project Statement: To design a high resolution digitally trimmable resistor. It should be capable of adjusting its resistance value by ±1%, should be re-trimmable infinitely many times.
The requirements of this project are the following:
Assumptions
Limitations
minimized
January
Week of the 13th Week of the 20th Week of the 27th
February
Week of the 3rd Week of the 10th Week of the 17th
March
LOR IPS DOL
April
LOR IPS DOL
Research Ideate Development Documentation/ presentation Administrative Q1
LOR IPS DOL
Q2
LOR IPS DOL
Q3
LOR IPS DOL
Q4
LOR IPS DOL
Lorem ipsum Lorem ipsum Lorem ipsum Lorem ipsum Lorem ipsum Q1
January February March
Q2
April May June
Q3
July August September
Q4
October November December
Research Ideate Development Presentation Administrative
231 days 161 days 21 days 2/3 - 9/14 1/20
74 days 3/2 - 3/30 8/24
16 days 26 days 11/9
4/10 - 4/26
Currently trimming resistors in IC is done with various methods.
○ Series Resistor Structure - Utilizes resistors in series ○ Parallel Resistor Structure - Utilizes resistors in parallel
Series Structure: Shortcomings:
mosfets.
temperature coefficients which don’t cancel out in voltage divider equation.
Parallel Design: Shortcomings:
applications.
Thermal Oven:
PAT NO US 8,242,876 B2
Laser Trim:
https://www.susumu.co.jp/usa/tech/know_how_05.php
Ladder Structure: Theory:
won’t be as prominent?
Matrix Structure:
Theory:
switches
Theory:
temperature coefficient and one with negative temperature coefficient.
coefficients would cancel.
Theory:
temperature coefficient and one with negative temperature coefficient.
coefficients would cancel.
Definition of TCR:
properties
Temperature Dependent Resistance Equation (from Cadence): R(T) = R(tnom) * [1 + tc1 * (T - tnom) + tc2 * (T - tnom)^2] Without specifying parameters in Virtuoso Instances, Cadence will assume the TCR to be 0.
Tested TCR for different Energy barrier levels for a p+ polysilicon resistor:
°Kelvin
Understanding resistivity of integrated resistors:
Energy Barrier is a function of grain size and carrier concentration.
Temperature(°C) Temperature(°C)
TCR(ppm/°C) @ Various Energy Barriers Resistance(Ohms)
Testing a resistor with TCR: -250 ppm/°C @ 27°C.
Switches - OFF Switches - ON
Calculated using resistor components with a TCR of 500 ppm/°C @ 27 °C
Resistance(Ohms) Resistance(Ohms)
Temperature(°C) Temperature(°C) .
Switch - Off
Resistance(Ohms) Resistance(Ohms)
Switch - On
Calculated using resistor components with a TCR of 500 ppm/°C @ 27 °C
Technical issues we’ve encountered so far:
Google Meet
First meeting Personal Research Temperature Coefficient Circuit Designs
established in the first semester.
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This concludes our presentation for the first semester of senior design. A big thanks to professor Geiger for all of his advising throughout the semester. Also, thanks to Pallavi-Sugantha for her assistance with some Virtuoso questions. Thanks for listening!