Hierarchical Exact Symbolic Analysis y y of Large Analog - - PowerPoint PPT Presentation

Hierarchical Exact Symbolic Analysis y y

• f Large Analog Integrated Circuits By

Symbolic Stamps Symbolic Stamps

Hui Xu, Guoyong Shi and Xiaopeng Li School of Microelectronics, Shanghai Jiao Tong Univ. Shanghai, China P t ti t A i S th P ifi D i A t ti C f (ASPDAC) Presentation at Asia South-Pacific Design Automation Conference (ASPDAC), Yokohama, Jan. 2010.

Contents Contents

• Motivation and Background
• The Idea of “Symbolic Stamp”

The Idea of Symbolic Stamp

• Implementation
• Experimental Results
• Conclusion
• Conclusion

2011-11-25 2

Motivation

Small Case Small Case

VDD

• Can be handled by existing exact symbolic analysis

method

M7 M8 M5 M1 M2 In- In+ Bias P Rz Cc Y X Out CL M4 M6 M3 2011-11-25 4

Large Case Large Case

• Cannot be handled by existing exact symbolic analysis

method

2011-11-25 5

Possible Application Possible Application

• Graphical Sensitivity Analysis[16]

Date 2011-11-25 6

[16] D. Ma, G. Shi, and A. Lee, “A design platform for analog device size sensitivity analysis and visualization,” in Proc. Asia Pacific Conference on Circuits and Systems (APCCAS), Malaysia, Dec. 2010

Motivation: Exact Analysis Motivation: Exact Analysis

• Many circuit characteristics (sensitivity, poles, zeros)

require an “exact” symbolic expression of H(s).

• Exact symbolic analysis of large analog circuits (20

~50 MOSFETs) is not easy.

Sensitivity Netlist

Symbolic analysis

H(s; p1, p2, ...)

Pole/Zero

y engine

Optimization

2011-11-25 7

Optimization

Symbolic Analysis Symbolic Analysis

Cons Pros

2011-11-25 8

Representative Methods

• Algebraic Methods – Determinant Decision Diagram[15]

Representative Methods

1 2

1 1 1 1 1 R R v v R R                       

to Matrix Algorithm

Data St t

Vs R C 1 2

Graph based Methods

G h P i D i i Di

[16]

1

s s

R R i v                  

Struct

s

• Graph-based Methods – Graph Pair Decision Diagram[16]

R

+

1 2 1/R 1 2 2

to Graph Algorithm

Data Struct

Vs C

• Vo

CS Vs Vc

[15] C.-J. Shi and X.-D. Tan, “Canonical symbolic analysis of large analog circuits with determinant decision diagrams,” IEEE Trans. on Computer-Aided Design,

• vol. 19, no. 1, pp. 1-18, Jan., 2000.

[16] G. Shi, W. Chen and C.-J. Shi, “A Graph Reduction Approach to Symbolic Circuit Analysis,” in Proc. Asia and South-Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, pp. 197-202, Jan., 2007.

2011-11-25 9

From Binary Tree to BDD From Binary Tree to BDD

• Binary Tree

1 2 3 1 2 3 1 2 3 1 2 3 1 2 3

( , , ) f x x x x x x x x x x x x x x x    

2011-11-25 10

[14] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. Comput., vol. C-37, pp. 677-691, Aug., 1986.

Reduced Ordered BDD Reduced Ordered BDD

Canonical and Compact!

1 1 1

Order: x1 > x2 > x3

1 1 1 1 1 1

1 2 3 1 2 3 1 2 3 1 2 3 1 2 3

( , , ) f x x x x x x x x x x x x x x x    

1 2 3 1 2 3 1 2 2 3

( , , ) f x x x x x x x x x x   

[14] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. Comput., vol. C-37, pp. 677-691, Aug., 1986.

2011-11-25 11

Determinant Decision Diagram Determinant Decision Diagram

R d i b BDD

• Represent a determinant by BDD
• Treat Laplace Expansion as binary decisions

a d c

1 edge 0 edge

det( ) a b c d e A

d c g f b

det( ) A f g h i j 

j i e

adgj adhi aefj bcgj cbih     

h 1

2011-11-25 12

1

Minor Sharing[25] Minor Sharing[25]

b c d e a c d e f g h i j

b d e c

d e

a d c

d e f c g h i j

d e f g h i j

d c g f b

b f g h i j

g h i j

j i e

j

h 1

2011-11-25 13

1

[25] G. Shi, “A simple implementation of determinant decision diagram,” in Proc. International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 2010.

Graph Pair Reduction Diagram Graph Pair Reduction Diagram

• Represent the transfer function by BDD
• Treat Spanning-Tree Enumeration as binary decisions

x + + R R C + + +

Vs R C

+

Vo

1 2

C

• +
• 1

2011-11-25 14

Graph Pair Sharing[16] Graph Pair Sharing[16]

R 1 2 1 R 2 C Vc Vs 1 2 1 C Vs 2

x

1/R CS Vs Vc 1 2 2 R 2 R C 2 R C 2

x R R + +

R C R 1 2 2

R R C + + +

C C

C

• +

1

2011-11-25 15

[16] G. Shi, W. Chen, and C.-J. R. Shi, “A graph reduction approach to symbolic circuit analysis,” in Proc. Asia South-Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan. 2007, pp. 197–202.

Hash Mechanisms Hash Mechanisms

• DDD – By Hashing Minors

Minor 1 Minor 2 Minor 3 Minor 1 Minor 2 Minor 3 g h i j

b f g h d e f g h

• GPDD – By Hashing subgraphs

i j

i j i j

• GPDD – By Hashing subgraphs

Graph Pair 1 Graph Pair 2 Graph Pair 3

R

C 2

R

C 2

R

C 2 R 1 C 2 C 2

2011-11-25 16

Idea of “Symbolic Stamp”

Symbolic Stamp Symbolic Stamp

VDD M7 M8 M5 M1 M2 In- In+ Bias Out P M4 M6 Rz Cc Y M3 X CL M4 M6 M3

All MOSFET th ll i l  All MOSFETs use the same small-signal model!  Circuits are naturally hierarchical!

2011-11-25 18

Assembling Symbolic Stamps Assembling Symbolic Stamps

A

p1 p2

C

p2 p1

1 3

1 2 3 4 n n n n

4

B

p2

11 12 11 12

1 2 3

A A B B C C

n y y n y y

B

p1

11 12 21 21 21 22 22 22

3 4

C C A B C A B C

n y y n y y y y y y  

2 DDD Routine

2011-11-25 19

Procedure

• 2. Build symbolic stamp of each sub-block

A multi-root GRDD containing the 4 y- parameters

1/ 1/ R R    

GPDD

11 12 21 22

1/ 1/ 1/ 1/ y y R R y y R R               

Date 2011-11-25

Symbolic R Stamp (y ) Symbolic R Stamp (y11)

+

it

1 1

y11

R Vt

+ 1

R Vs n Cc n R Vs Cc

X

• 1

1

+

R

R R

+ +

1

+

1 1

1

+

Date 2011-11-25 Page 21

Symbolic R Stamp (y ) Symbolic R Stamp (y12)

+

it

2

R Vt

+

1

y12

Cc 1 R Vs 2 Cc 1 R Vs 2 0 -

X

y12

1 R

• +

R

R 2

1

+

1

• Date 2011-11-25

Page 22

1

Symbolic Stamp Computation Symbolic Stamp Computation

+ i1 i2 G = 1/R V1 V2 + +

1 2 11 12 21 22

y y G G y y y G G                

• y12

y21 y11 y22

+ + + + + + G G + + + + 1

• +

+ +

2011-11-25 23

Four-root GPDD for R symbolic stamp

Why GPDD for symbolic stamp Why GPDD for symbolic stamp

11 12

1 2 3 4 1

A A

n n n n n y y

GPDD DDD

G = 1/R V1 V2 + i1 i2

11 12 11 12 11 12

1 2 3

B B C C

n y y n y y n y y

V1 V2

• 21

21 21 22 22 22

4

A B C A B C

n y y y y y y  

Dire Ind ect Link direct Link

G S

k

2011-11-25 24

Hierarchical Structure Hierarchical Structure

H( ) H(s) freq

MNA Matrix (DDD)

HYBRIDSIM Simulator

Sub-circuit 1 Symbolic Stamp (Multi-root GPDD) Sub-circuit 2 Symbolic Stamp (Multi-root GPDD) Sub-circuit 3 Symbolic Stamp (Multi-root GPDD) DEVICE DEVICE DEVICE DEVICE

2011-11-25 25

Experimental Results

Implementation Flow Implementation Flow

.Op

New

Will be integrated into our program in the future

Netlist

(Now use HSPICE)

Small Signal Model Extraction

New Netlist

Analog Design GUI Symbolic analysis

( ; ) H s p 

Analog Design GUI

H(s)

analysis engine

( ; ) H s p

freq

2011-11-25 27

q

Platform Environment Platform Environment

• Programming Language and tools:

– C++

• Test cases are running on an AMD Athlon64

Test cases are running on an AMD Athlon64 2.20GHz processor with 2GB memory

• HSPICE 2007 is used for DC operating point

l i analysis

2011-11-25 28

Benchmark 1 Benchmark 1

• A rail-to-rail Miller MOSFET amplifier containing

24 transistors

2011-11-25 29

Benchmark 2 Benchmark 2

• A MOSFET operational amplifier containing 44

transistors[26]

[26] T McConaghy and G G E Gielen “Globally reliable variation aware sizing of analog integrated circuits via response surfaces and

2011-11-25 30

[26] T. McConaghy and G. G. E. Gielen, Globally reliable variation-aware sizing of analog integrated circuits via response surfaces and structural homotopy,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1627–1640, Nov. 2009.

MOSFET Small Signal Model MOSFET Small Signal Model

• All MOSFETs share one symbolic stamp of

the model the model

12 symbols 481 vertices in 481 vertices in the multi-root GRDD

Date 2011-11-25 Page 31

Test Settings Test Settings

• Partition Strategy

– MOSFET as a sub-circuit – Maximize the sharing

• Small-signal Model

– SPICE LEVEL 3[23]

2011-11-25 32

[23] A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits using SPICE2,” EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M80/7, 1980.

Performance Summary Performance Summary

Op-amp Circuit #Device (T) #Symb for GPDD #Symb for DDD MNA Matrix Size |GPDD| (vertices) |DDD| (vertices) Time (sec.) Memory (MB)

Case 1 24 12 104 18x18 481 70,129 1.81 70 Case 2 44 12 140 28x28 481 45,716 1.50 91

• Remarks

– Both DDD-based (newly implemented[25]) and GPDD-based non- hierarchical simulator[16] cannot handle these two circuits hierarchical simulator[16] cannot handle these two circuits.

[16] G. Shi, W. Chen, and C.-J. R. Shi, “A graph reduction approach to symbolic circuit analysis,” in Proc. Asia South-Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan. 2007, pp. 197–202. [25] G Shi “A i l i l t ti f d t i t d i i di ” i P I t ti l C f C t Aid d D i

2011-11-25 33

[25] G. Shi, “A simple implementation of determinant decision diagram,” in Proc. International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 2010.

F R Frequency Response

 Benchmark 1 (24-trans rail to rail MOS amplifier)

Date 2011-11-25 Page 34

Conclusion Conclusion

• Proposed a “symbolic stamp” approach to

hierarchical analysis y

• Investigated an efficient implementation

I d th it f “ t” l i

• Improved the capacity for “exact” analysis
• More applications for design optimization
• e app cat o s o des g
• pt

at o in the future

2011-11-25 35

Thanks

Q & A Q & A