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Handheld Device Architectures: Are We Doing Enough?
Manu Awasthi Ashoka University
Handheld Device Architectures: Are We Doing Enough? Manu Awasthi - - PowerPoint PPT Presentation
Handheld Device Architectures: Are We Doing Enough? Manu Awasthi - - PowerPoint PPT Presentation
Handheld Device Architectures: Are We Doing Enough? Manu Awasthi Ashoka University Handheld Devices Android Versions https://www.counterpointresearch.com/can-android-o- de-fragment-android/ Memory Usage
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Android Versions
https://www.counterpointresearch.com/can-android-o- de-fragment-android/
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Memory Usage
https://eitik.com/17-android-browser-tested-for-memory-usage-in-2018/
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A Few Trends
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Mobile Architecture Research
- Mobile computing research: 1% of research papers published each
focus on mobile computing.
- Lack of tools
- V. J. Reddi, H. Yoon, and A. Knies, “Two billion devices and counting,” IEEE Micro, vol. 38, no. 1, pp. 6–21, January/February 2018.
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What is needed?
- Tool and Simulators
- Benchmarks
BBench (Michigan) AsimBench (ICT, China)
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Current Status
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Android Emulator
Android Open Source Project (AOSP)
Android Virtual Device (AVD)
Android Emulator
Device Behavior
How do we leverage the existing ecosystem to study memory behavior of Android apps?
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META: Tool Design
MobiCom 2018
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Tracer Module - Modifications in QEMU
Modified Translation Path
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Raw Traces
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META: Tool Design : Cache Module
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Cache Simulation Module
L1 and L2 Cache hit rates available after running a calculator on a range of android versions from Android 4 (Kitkat) to Android 7 (Nougat).
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META: Tool Design: Memory Module
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NVMain Integration
- NVMain : cycle-level main memory
simulator
- Can simulate DRAM, emerging non-
volatile memories at the architectural level.
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Phase change memory, STT-RAM
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Potential Use-cases
- Trace Generation
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The traces can also be used to analyze instruction distribution profile.
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Creation of synthetic inputs to models based on real instruction profiles
- Cache Hierarchy Modeling
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A custom, N-level cache hierarchy
- DRAM, Non-volatile, Hybrid Memory Simulation
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NVMain can model most technologies
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Trends in Handheld Devices
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https://thehackernews.com/2015/09/6gb-ram-smartphone.html
http://www.es.ele.tue.nl/~kgoossens/Chandrasekar14PHD.pdf https://www.pwc.com/gx/en/technology/mobile-innovation/assets/pwc-dram-memory.pdf
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Handhelds and Smartphones
19 Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications, IEEE Micro, Vol 34, 2014
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Main Memory in Handhelds
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MC Core 1 Core 2 Core 3 Core 4 Fabric Fabric GPU Camera Display
Audio
Sensors Modem
DRAM DRAM
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Handheld Applications
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If frequently accessed data can be concentrated to the fastest regions of a hybrid memory hierarchy, memory system’s energy consumption can be reduced significantly, without any significant loss in performance and user experience.
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Hybrid Memory Architectures for Handhelds
Total Physical Address Space 0 GB 4 GB Sub Address Space Sub Address Space Sub Address Space
DRAM Mem Tech 2 NVM
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Hybrid Main Memory in Handhelds
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MC Core 1 Core 2 Core 3 Core 4 Fabric Fabric GPU Camera Display
Audio
Sensors Modem
DRAM NVM
MC
DATE 2018
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Hybrid Main Memory in Handhelds
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MC
Core 1 Core 2 Core 3 Core 4 Fabric Fabric GPU Camera Display
Audio
Sensors Modem
DR AM
N V M
MC MC MC
N V M
DR AM
DATE 2018
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Results
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Results – 4 Controllers
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Key Takeways
- Research into handheld devices architectures is important, more so in
the era of wearables
- Memory sub-system is becoming increasingly important, even in handheld
- Need tools, benchmarks to carry research forward
- META – one step in that direction
- NVMs will eventually be integrated into memory hierarchy
- Mechanisms to provide access to high capacity, low latency memories might
require intelligent data management
- H/W – S/W co-design is better than one or the other.
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