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Introduction TLM RTC Abstract Interpretation Conclusion Habilitation Diriger des Recherches High-level Models for Embedded Systems Matthieu Moy Verimag (Grenoble INP) Grenoble, France March 13 th 2014 Jury: Grard Berry Professeur au

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Introduction TLM RTC Abstract Interpretation Conclusion

Habilitation à Diriger des Recherches High-level Models for Embedded Systems

Matthieu Moy

Verimag (Grenoble INP) Grenoble, France

March 13th 2014

Jury: Gérard Berry Professeur au Collège de France Reviewer Rolf Drechsler Professor at TU Bremen, Germany Reviewer Marco Roveri Senior Researcher, Fondazione Bruno Kessler, Italy Reviewer Samarjit Chakraborty Professor at TU Muchen, Germany Examiner Benoît Dupont de Dinechin Directeur Technique, Kalray, France Examiner Frédéric Pétrot Professeur à Grenoble INP , France Examiner Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 1 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag Research at Verimag

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag Research at Verimag The SystemC guy

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag Research at Verimag The SystemC guy The RTC guy

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag Research at Verimag The SystemC guy The RTC guy

Also works

  • n abstract

interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

About Me

Teaching at Ensimag Research at Verimag The SystemC guy The RTC guy

Also works

  • n abstract

interpretation

The macarons guy

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 2 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

What Are Processors For?

Computers

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 3 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

What Are Processors For?

Computers Embedded systems

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 3 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

What Are Processors For?

Computers Embedded systems Vertebrate Insects

Source: http://skepchick.org/2013/03/planet-of-the-arthropods/ Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 3 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

What Are Processors For?

Computers ≈ 2% Embedded systems ≈ 98% Vertebrate ≈ 4% Insects ≈ 96%

Source: http://skepchick.org/2013/03/planet-of-the-arthropods/ Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 3 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Prehistory: My Phone (2010)

Source: http://www.embeddedinsights.com/epd/samsung/samsung-s5pc110.php Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 4 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Another Typical Embedded System: my New Camera

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 5 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Another Typical Embedded System: my New Camera

Firmware

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 5 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Another Typical Embedded System: my New Camera

Firmware A Firmware B

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 5 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Another Typical Embedded System: my New Camera

Firmware A Firmware B

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 5 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Modern Systems-on-a-Chip

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 6 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Modern Systems-on-a-Chip

Software Hardware

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 6 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 1: Functional Correctness

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 7 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 1: Functional Correctness

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 7 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 1: Functional Correctness

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 7 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation cost > 1,000,000 $ !

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development Model

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development Model Integration Factory Validation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development Model Integration Factory Validation

gain

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 3: Timing

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 9 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

50-130 watt

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

20-30 watt 50-130 watt

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

20 watt 20-30 watt 50-130 watt

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

< 1 watt 20 watt 20-30 watt 50-130 watt

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 5: Simulation speed

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 11 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Issue 6: Model Faithfulness

model actual

Extra behaviors

  • f the model

(A) Unmodeled behaviors (B) Exactly modeled behaviors (C)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 12 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Models and Virtual Prototypes Model/Prototype Real system

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 13 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Models and Virtual Prototypes Model/Prototype Real system

Synthesize

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 13 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Models and Virtual Prototypes Model/Prototype Real system

(Synthesize)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 13 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Models and Virtual Prototypes Model/Prototype Real system

(Synthesize) Compare Use as specification ...

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 13 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Context and Collaborations of my Work

2002 2005 2010 2014 My Ph.D OpenTLM

  • G. Funchal Ph.D

FoToVP HELP Combest

CESyMPA

OpenES

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Introduction TLM RTC Abstract Interpretation Conclusion

Context and Collaborations of my Work

2002 2005 2010 2014 My Ph.D OpenTLM

  • G. Funchal Ph.D

FoToVP HELP Combest

CESyMPA

OpenES STMicroelectronics

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Introduction TLM RTC Abstract Interpretation Conclusion

Context and Collaborations of my Work

2002 2005 2010 2014 My Ph.D OpenTLM

  • G. Funchal Ph.D

FoToVP HELP Combest

CESyMPA

OpenES STMicroelectronics Docea Power ETHZ TIMA CEA-LETI IRISA INRIA Rhone Alpes

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 14 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 15 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 15 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

TLM and Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development Model Integration Factory Validation

gain

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 16 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

TLM and Software Development

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Model based

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Integration Factory Validation

gain

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 16 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 17 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow

≈ 1000 Faster than low-level simulations (RTL)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 17 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow

≈ 1000 Faster than low-level simulations (RTL)

In production in the industry

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 17 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Content of a TLM Model

Model what is needed for Software Execution:

◮ Processors ◮ Address-map ◮ Concurrency

... and only that.

◮ No micro-architecture ◮ No bus protocol ◮ No pipeline ◮ No physical clock ◮ . . .

read

  • addr
  • data

write

  • addr
  • data

addr data

Standard for TLM = SystemC (IEEE1666)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 18 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

An Example TLM Model

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 19 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

Virtual Prototype for Software Development

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 20 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

?

=

Virtual Prototype for Software Development

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 20 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

?

=

Virtual Prototype for Software Development

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 20 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

?

=

Virtual Prototype for Software Development

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 20 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

?

=

Virtual Prototype for Software Development

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

Unmodified Software

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 20 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Non-Functional Models

Timing, Power consumption, Temperature Estimation

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 21 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Non-Functional Models

Timing, Power consumption, Temperature Estimation

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

30 20 10 10 20 30 40 50 60

Estimated Time/Power/Temperature

30 20 10 10 20 30 40 50 60

Actual

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 21 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Non-Functional Models

Timing, Power consumption, Temperature Estimation

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

TLM

30 20 10 10 20 30 40 50 60

Estimated Time/Power/Temperature

30 20 10 10 20 30 40 50 60

Actual

Unmodified Power/Temperature-Aware Software

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 21 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 22 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 22 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 22 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

SystemC: Simple Example

A B

int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob"); /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0; } struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); } SC_CTOR(A) { SC_THREAD(thread); } };

Compilable with any C++ compiler

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 23 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang++ ≈ 400,000 LOC)

2

Architecture built at runtime, with C++ code

int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob"); /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0; } struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); } SC_CTOR(A) { SC_THREAD(thread); } }; Guillaume Sergent Kevin Marquet

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 24 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang++ ≈ 400,000 LOC) Write a C++ front-end or reuse one (g++, clang++, EDG, . . . )

2

Architecture built at runtime, with C++ code Analyze elaboration phase or execute it

int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob"); /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0; } struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); } SC_CTOR(A) { SC_THREAD(thread); } }; Guillaume Sergent Kevin Marquet

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 24 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang++ ≈ 400,000 LOC) Write a C++ front-end or reuse one (g++, clang++, EDG, . . . )

2

Architecture built at runtime, with C++ code Analyze elaboration phase or execute it

int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob"); /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0; } struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); } SC_CTOR(A) { SC_THREAD(thread); } };

Static Approaches Dynamic Approaches

Guillaume Sergent Kevin Marquet

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 24 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 25 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 25 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Formal Verification: Encoding Approaches

SystemC program Encoding Property Built-in knowledge

  • f SystemC

Formal language Existing verifier Lesar, Nbac (Lustre) SMV SPIN (Promela) Yes/No/Maybe Kevin Marquet

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 26 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 27 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models Giovanni Funchal

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 27 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models Nabila Abdessaied Giovanni Funchal

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 27 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 27 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Simulation Parallelization

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 28 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Simulation Parallelization

SystemC uses co-routine semantics (Sequential)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 28 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Problems and Solutions for Parallel Execution of SystemC/TLM

(1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 29 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Problems and Solutions for Parallel Execution of SystemC/TLM

(1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable)

No efficient and automatic solution for SystemC/TLM

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 29 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Problems and Solutions for Parallel Execution of SystemC/TLM

(1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable)

No efficient and automatic solution for SystemC/TLM Our proposal = new constructs: Desynchronisation (1) / Synchronisation (2)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 29 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: The Idea

SC_THREAD_1 SC_THREAD_2 . . . SC_THREAD_N OS thread_1 OS thread_2 OS thread_N SystemC OS Thread Unmodified SystemC Computations delegated to external threads Weak synchronization between SystemC and tasks with duration

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 30 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Simulated Time in SystemC and SC-DURING

SystemC

SC-DURING

A B P Q

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 31 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Simulated Time in SystemC and SC-DURING

SystemC

SC-DURING

A B P Q Process A: // computation f(); // time taken by f wait(20, SC_NS); f() wait(20)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 31 / 51 >

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Introduction TLM RTC Abstract Interpretation Conclusion

Simulated Time in SystemC and SC-DURING

SystemC

SC-DURING

A B P Q Process A: // computation f(); // time taken by f wait(20, SC_NS); f() wait(20) Process P: g(); wait(20, SC_NS); g() wait(20)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 31 / 51 >

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SLIDE 85

Introduction TLM RTC Abstract Interpretation Conclusion

Simulated Time in SystemC and SC-DURING

SystemC

SC-DURING

A B P Q Process A: // computation f(); // time taken by f wait(20, SC_NS); f() wait(20) Process P: g(); wait(20, SC_NS); during(15, SC_NS, h); g() wait(20) h()

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 31 / 51 >

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SLIDE 86

Introduction TLM RTC Abstract Interpretation Conclusion

Simulated Time in SystemC and SC-DURING

SystemC

SC-DURING

A B P Q Process A: // computation f(); // time taken by f wait(20, SC_NS); f() wait(20) Process P: g(); wait(20, SC_NS); during(15, SC_NS, h); g() wait(20) h() i() j()

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SLIDE 87

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread

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SLIDE 88

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread during(d, f);

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SLIDE 89

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f

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SLIDE 90

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f 2 wait(d)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 32 / 51 >

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SLIDE 91

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f 2 wait(d)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 32 / 51 >

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SLIDE 92

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f 2 wait(d) join() 3

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 32 / 51 >

slide-93
SLIDE 93

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f 2 wait(d) join() 3

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 32 / 51 >

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SLIDE 94

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Sketch of Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); create thread f 2 wait(d) join() 3

+ thread pooling + richer synchronization API

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 32 / 51 >

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SLIDE 95

Introduction TLM RTC Abstract Interpretation Conclusion

SC-DURING: Results

2 4 6 8 10 12 14 10 20 30 40 50 60

Speedup Number of CPUs in the platform

Loosely-Timed Models Fine-grain Timing Test machine has 4 × 12 = 48 cores Swadhin Mangaraj

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 33 / 51 >

slide-96
SLIDE 96

Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 34 / 51 >

slide-97
SLIDE 97

Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models Samuel Jones

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 34 / 51 >

slide-98
SLIDE 98

Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 34 / 51 >

slide-99
SLIDE 99

Introduction TLM RTC Abstract Interpretation Conclusion

SystemC and Extra-Functional Solver Cosimulation

SystemC Power and Temperature Solver (ATMI, ACEplorer) Power States Temperature

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 35 / 51 >

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SLIDE 100

Introduction TLM RTC Abstract Interpretation Conclusion

SystemC and Extra-Functional Solver Cosimulation

SystemC Power and Temperature Solver (ATMI, ACEplorer) Power States Temperature Tayeb Bouhadiba Claude Helmstetter

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 35 / 51 >

slide-101
SLIDE 101

Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 36 / 51 >

slide-102
SLIDE 102

Introduction TLM RTC Abstract Interpretation Conclusion

Contributions on TLM

Correctness Power/Temperature Timing Faithfulness Simulation Speed

Early Software Execution Optimizing Compiler Compilation Formal Verification Smart FIFO Parallelization jTLM Memory Models Functional/extra-functional Cosimulation Traffic models

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 36 / 51 >

slide-103
SLIDE 103

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

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slide-104
SLIDE 104

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 37 / 51 >

slide-105
SLIDE 105

Introduction TLM RTC Abstract Interpretation Conclusion

Precision Vs Algorithmic Complexity

Analysability useless zone Unreachable zone Expressivity States states No Models Detailed Computational Analytical Models Calculus Checking Model Real−Time Simulation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 38 / 51 >

slide-106
SLIDE 106

Introduction TLM RTC Abstract Interpretation Conclusion

Precision Vs Algorithmic Complexity

Analysability useless zone Unreachable zone Expressivity States states No Models Detailed Computational Analytical Models Calculus Checking Model Real−Time Simulation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 38 / 51 >

slide-107
SLIDE 107

Introduction TLM RTC Abstract Interpretation Conclusion

Modular Performance Analysis (MPA): The Big Picture

[Thiele et al.]

input

Component1 Component2

  • utput

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 39 / 51 >

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SLIDE 108

Introduction TLM RTC Abstract Interpretation Conclusion

Modular Performance Analysis (MPA): The Big Picture

[Thiele et al.]

input

Component1 Component2

  • utput

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 39 / 51 >

slide-109
SLIDE 109

Introduction TLM RTC Abstract Interpretation Conclusion

Modular Performance Analysis (MPA): The Big Picture

[Thiele et al.]

input

Component1 Component2

  • utput

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slide-110
SLIDE 110

Introduction TLM RTC Abstract Interpretation Conclusion

Modular Performance Analysis (MPA): The Big Picture

[Thiele et al.]

input

⊗, ⊘, ⊗ , ⊘ , . . . Component1 ⊗, ⊘, ⊗ , ⊘ , . . . Component2

  • utput

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 39 / 51 >

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SLIDE 111

Introduction TLM RTC Abstract Interpretation Conclusion

Real-Time Calculus and Arrival Curves

δt

1 2 3 4 5

#events

1 2 3 4 5

αu αl αu(t) / αl(t) : min/max number of events in any window of duration t.

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 40 / 51 >

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SLIDE 112

Introduction TLM RTC Abstract Interpretation Conclusion

Interfacing with Timed Automata

[Chakraborty et al.]

RTC Richer Formalism Generator Component Observer

input: αi

  • utput: αo

compilation formal analysis

Yanhong Liu

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 41 / 51 >

slide-113
SLIDE 113

Introduction TLM RTC Abstract Interpretation Conclusion

Timed Automata Vs Abstract Interpretation and SMT-Solving

Large event counters Large timing constants Timed automata (Uppaal) SMT solving Abstract Interpretation ac2lus: use Lustre tools to analyze MPA components (Nbac = abstract interpretation, Kind = SMT solving)

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 42 / 51 >

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SLIDE 114

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

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slide-115
SLIDE 115

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

αl Deadline 6 pages written

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slide-116
SLIDE 116

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

αu αl One page per day Deadline 6 pages written

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 43 / 51 >

slide-117
SLIDE 117

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

αu αl One page per day Week-end Deadline 6 pages written

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 43 / 51 >

slide-118
SLIDE 118

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

αu αl One page per day Week-end Deadline 6 pages written Implicit constraint: maximal procrastination = 2 days

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 43 / 51 >

slide-119
SLIDE 119

Introduction TLM RTC Abstract Interpretation Conclusion

The Causality Problem

δt

1 2 3 4 5 6 7 8 9 10 11

#events

1 2 3 4 5 6 7

αu αl One page per day Week-end Deadline 6 pages written Causality closure = compute the implicit constraint automatically

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 43 / 51 >

slide-120
SLIDE 120

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 44 / 51 >

slide-121
SLIDE 121

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 44 / 51 >

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SLIDE 122

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation and PAGAI

$ pagai -i test.c void f() { int x = 0, y = 1; /* invariant: y = x + 1 y <= 102 y >= 1 */ while (x <= 100) { x++; y++; } } Julien Henry

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 45 / 51 >

slide-123
SLIDE 123

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

slide-124
SLIDE 124

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

slide-125
SLIDE 125

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

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slide-126
SLIDE 126

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

slide-127
SLIDE 127

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

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slide-128
SLIDE 128

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

#

= join

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

slide-129
SLIDE 129

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

#

= join

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slide-130
SLIDE 130

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

#

= join

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

slide-131
SLIDE 131

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

∇ = widening

#

= join

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

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SLIDE 132

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

∇ = widening

#

= join SMT formula “is there a feasible path that makes the candidate invariant grow?”

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

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SLIDE 133

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

∇ = widening

#

= join SMT formula “is there a feasible path that makes the candidate invariant grow?” Don’t consider if only activated because of ∇

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

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SLIDE 134

Introduction TLM RTC Abstract Interpretation Conclusion

Abstract Interpretation with PAGAI

[Cousot & Cousot]

∇ = widening

#

= join SMT formula “is there a feasible path that makes the candidate invariant grow?” Don’t consider if only activated because of ∇ Keep union symbolic

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 46 / 51 >

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SLIDE 135

Introduction TLM RTC Abstract Interpretation Conclusion

PAGAI: Results

Tested on real programs

Time (in seconds) Name kLOC |loops| S G PF C DIS a2ps 55 2012 23 74 34 115 162 gawk 59 902 15 46 12 40 50 gnuchess 38 1222 50 220 81 312 351 gnugo 83 2801 77 159 92 766 1493 grep 35 820 41 85 22 65 122 gzip 27 494 22 268 91 303 230 lapack 954 16422 294 3740 3773 8159 10351 make 34 993 67 108 53 109 257 tar 73 1712 37 218 115 253 396

Improves discovered invariants

2 4 6 8 10 12 14 16 18 G/S PF/S PF/G G+PF/PF G+PF/G G+PF/S DIS/G+PF percentage of control points

  • uncomparable

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 47 / 51 >

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SLIDE 136

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 48 / 51 >

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SLIDE 137

Introduction TLM RTC Abstract Interpretation Conclusion

Outline

SystemC/TLM Real-Time Calculus Abstract Interpretation Time to conclude...

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 48 / 51 >

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SLIDE 138

Introduction TLM RTC Abstract Interpretation Conclusion

Summary

Introduction TLM RTC Abstract Interpretation Conclusion

Issue 1: Functional Correctness

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 7 / 51 > Introduction TLM RTC Abstract Interpretation Conclusion

Issue 2: Early Software Development

Time Traditional Design-Flow Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation Model based Specification, Algorithm RTL Design Synthesis Software Development Model Integration Factory Validation gain Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 8 / 51 > Introduction TLM RTC Abstract Interpretation Conclusion

Issue 3: Timing

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 9 / 51 > Introduction TLM RTC Abstract Interpretation Conclusion

Issue 4: Power and Temperature

< 1 watt 20 watt 20-30 watt 50-130 watt Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 10 / 51 > Introduction TLM RTC Abstract Interpretation Conclusion

Issue 5: Simulation speed

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 11 / 51 > Introduction TLM RTC Abstract Interpretation Conclusion

Issue 6: Model Faithfulness

model actual Extra behaviors
  • f the model
(A) Unmodeled behaviors (B) Exactly modeled behaviors (C) Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 12 / 51 >

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 49 / 51 >

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SLIDE 139

Introduction TLM RTC Abstract Interpretation Conclusion

Scientific Production

Software Pinapa, PinaVM, PAGAI, LIBTLMPWT,

SC-DURING, ac2lus, ...

Papers 15 international conferences, 9 workshops, 1 book chapter, 1 journal. Trained students Completed: 1 Ph.D, 5 research master, 6 post-docs, 20 short internships Ongoing: 2 Ph.D, 2 research master, 3 short internships Ensimag course on SystemC/TLM

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 50 / 51 >

slide-140
SLIDE 140

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

(Slide from Laurent Maillet-Contoz)

slide-141
SLIDE 141

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

A common ground

  • Scientific context
  • Applicative context

(Slide from Laurent Maillet-Contoz)

slide-142
SLIDE 142

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

A common ground

  • Scientific context
  • Applicative context

A research subject covering shared interests

(Slide from Laurent Maillet-Contoz)

slide-143
SLIDE 143

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

Periodic exchanges and in-depth discussions In the long-term A common ground

  • Scientific context
  • Applicative context

A research subject covering shared interests

(Slide from Laurent Maillet-Contoz)

slide-144
SLIDE 144

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

Periodic exchanges and in-depth discussions In the long-term Concrete works to progress at each party’s own rythm and enrich the landscape (not everything will succeed) A common ground

  • Scientific context
  • Applicative context

A research subject covering shared interests

(Slide from Laurent Maillet-Contoz)

slide-145
SLIDE 145

Condition for Success of a Lab/Industry Cooperation

Suitable environment:

  • Shared motivation
  • Understanding and respect of

each party’s constraints

  • Legal framework
  • Bonus: geographic proximity

Periodic exchanges and in-depth discussions In the long-term Elements of solution that enrich both parties Next cooperation theme Concrete works to progress at each party’s own rythm and enrich the landscape (not everything will succeed) A common ground

  • Scientific context
  • Applicative context

A research subject covering shared interests

(Slide from Laurent Maillet-Contoz)

slide-146
SLIDE 146

Introduction TLM RTC Abstract Interpretation Conclusion

Prospects

SystemC/TLM Real-Time Calculus Abstract Interpretation

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 51 / 51 >

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SLIDE 147

Introduction TLM RTC Abstract Interpretation Conclusion

Prospects

SystemC/TLM Real-Time Calculus Abstract Interpretation Critical Systems

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 51 / 51 >

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SLIDE 148

Introduction TLM RTC Abstract Interpretation Conclusion

Questions?

SystemC/TLM Real-Time Calculus Abstract Interpretation Critical Systems

Thank You!

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 51 / 51 >

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SLIDE 149

Introduction TLM RTC Abstract Interpretation Conclusion

Supervised/Co-supervised Ph.D

Giovanni Funchal 2007 → 2011 CIFRE STMicroelectronics co-supervised with Florence Maraninchi Julien Henry 2011 → present co-supervised with David Monniaux Swadhin Mangaraj 2013 → present OpenES european project

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Introduction TLM RTC Abstract Interpretation Conclusion

Sources

http://en.wikipedia.org/wiki/File:Diopsis.jpg (Peter John Bishop, CC Attribution-Share Alike 3.0 Unported) http://www.fotopedia.com/items/flickr-367843750 (oskay@fotopedia, CC Attribution 2.0 Generic) http://www.flickr.com/photos/artbystevejohnson/4654013143/ (Steve Johnson, CC Attribution 2.0 Generic) http://xkcd.com/612/ (Randall Munroe, CC Attribution 2.0 Generic) http://uk.wikipedia.org/wiki/%D0%A4%D0%B0%D0%B9%D0%BB:Soldering_iron_%28UK_Plug%29. jpg (oomlout, CC Attribution Share-Alike 2.0 Generic) Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 51 / 51 >

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Sources

http://commons.wikimedia.org/wiki/File:Intel_Core_I7-920_Boxed_-_15.JPG (Alan Lorenzo, CC Attribution-Share Alike 3.0 Unported) http://commons.wikimedia.org/wiki/File:Choc_cake_ill_01.svg (Kilom691, CC Attribution-Share Alike 3.0 Unported) http://en.wikipedia.org/wiki/File:Singapore_Airlines_A380_9V-SKH.jpg (Simon_sees, CC Attribution 2.0 Generic) http://opensource.org/logo-usage-guidelines (OSI, Creative Commons Attribution 3.0 License)

+ Open Clip Art public domain pictures

Matthieu Moy (Verimag) High-level Models for Embedded Systems March 13th 2014 < 51 / 51 >