Packaging for Power Electronics Habilitation Diriger des Recherches - - PowerPoint PPT Presentation

Packaging for Power Electronics

“Habilitation à Diriger des Recherches” Cyril BUTTAY

Laboratoire Ampère, Lyon, France

2015

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Outline

Professional Record Background Contributions Perspectives Conclusion

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Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

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History

1996 – 2001: Electrical Engineer training (INSA Lyon) 2001 – 2004: PhD thesis (CIFRE grant with Valeo) at CEGELY 2004 – 2005: Teaching assistant (ATER at INSA Lyon), LGEF 2005 – 2007: Research Associate with Sheffield and Nottingham Universities 2008 – . . . : Researcher (Chargé de recherche) with CNRS. ➜ From pure Electrical Engineering to Packaging

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Teaching

Type of classes

Lab/Projects 59% Tutorials 6% Lectures 4% Administrative 31%

Student Level

(Licence/Bachelor or Master)

L1 27% L2 16% L3 24% M1 11% M2 21%

Total 2001–2015: 645 h

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Publications

2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2 4 6 8 10 Count

conferences journals

WOS Google Citations 182 610 h-index 6 12

◮ Journals:

◮ 9 IEEE ◮ 6 Elsevier

◮ 2 invited conferences ◮ 2008: Starting with CNRS ◮ 2013-2014: HDR writing-up

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Supervision

2 9 2 1 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 Master Master Master Master License PhD PhD PhD PhD PhD

• A. Masson

A.-S. Podlejski

• V. Dos Santos
• W. Sabbah
• C. Yu
• B. Mouawad
• L. Ruffeil
• S. Hascoet
• I. Dchar
• R. Riva
• H. Reynes
• N. Qorchi
• H. Dung
• J. Billore
• M. Kamden
• D. Moureaux
• E. Rjeilly
• R. Caillaud
• J. Zaraket
• R. Leite
• H. Ben Omar

◮ Shared supervision, various degrees ◮ Funded by the industry or by research projects ◮ Increase in Master’s projects

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Research Projects

2009 2010 2011 2012 2013 2014 2015

EPAHT ETHAER BQR CIFRE Industry Project ECLIPSE ARC THOR Industry Project BQR

• Ind. Project

ACCITE SuMeCe

• Ind. Project

Supergrid Genome

◮ Some projects with lower involvment not mentionned ◮ Various funding schemes:

◮ European: Euripides-Catrene (THOR) ◮ National: Agency for Research (ETHAER, ECLIPSE), Aerospace

and Space –FNRAE– (EPAHT, ACCITE)

◮ Local fundings: BQR, Carnot institute (SuMeCe) ◮ Direct funding by the industry (5 companies) 6 / 45

Others activities

◮ In the lab

◮ Member of the laboratory board ◮ Installation and management of shared equipment: ◮ Packaging lab (≈ 300kC) ◮ Computer cluster (2009–2014)

◮ In the research community

◮ Reviewer for journals/conferences (20-30 publications/year) ◮ Reviewer for projects proposals (Cleansky, 7 days) ◮ Member of 3 selection panels (hiring of lecturers) ◮ Member of PhD jurys (10) ◮ Member of an evaluation committee (LN2, Sherbrooke) ◮ Management of the “3DPHI” platform on power integration

(Toulouse) with 2 colleagues.

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Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

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The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

The Power Module

◮ Many functions:

◮ Thermal management ◮ Electrical insulation ◮ Interconnects ◮ Mechanical/chemical protection

◮ Many materials:

◮ Ceramics ◮ Metals ◮ Organics. . . 8 / 45

Operating Temperature Limits

0°C 500°C 1000°C 1500°C 2000°C 2500°C 3000°C 10 V 100 V 1 kV 10 kV 100 kV 1 MV Junction temperature Breakdown voltage Silicon 3C−SiC 6H−SiC 4H−SiC 2H−GaN Diamond

Source: C. Raynaud et al. “Comparison of high voltage and high temperature performances of wide bandgap semiconductors for vertical power devices” Diamond and Related Materials, 2010, 19, 1-6

Some limits: 660° C Aluminium melts ≈ 300° C Die Solder melts 200 – 250 ° C Silicone gel degrades ≈ 200° C Board solder melts

◮ For Wide-Bandgap devices, limits set by packaging ◮ Additional packaging issues with thermal cycling

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Effect of the Packaging on Electrical Performance

RGl Tl VDRl RGh Th VDRh VIn IOut

◮ Stray inductances cause ringing and switching losses ◮ Parasitic capacitances cause common-mode current ◮ Both are caused by packaging

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Effect of the Packaging on Electrical Performance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ Stray inductances cause ringing and switching losses ◮ Parasitic capacitances cause common-mode current ◮ Both are caused by packaging

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Effect of the Packaging on Electrical Performance – 2

0 J 500 uJ 1 mJ 0 H 20 nH 40 nH 60 nH 80 nH 100 nH 120 nH Switching energy (J) Drain inductance (H) Simulations at I0 = 100 A Energy stored in the drain inductance

◮ Low voltage switching cell (30 V Si MOSFETs) simulations ◮ Most of the losses can be attributed to circuit layout ◮ Here all stray inductances 1 nH, except LD

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Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

11 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

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Applications of High Temperature Electronics

◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225°

C)

◮ Long operating life (up to 30 years)

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Applications of High Temperature Electronics

◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225°

C)

◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical

and internal combustion engines.

◮ Cooling fluid temperature: 120 °

C

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Applications of High Temperature Electronics

◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225°

C)

◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical

and internal combustion engines.

◮ Cooling fluid temperature: 120 °

C

◮ NASA mission to Venus: up to 480°

C

◮ Mission to Jupiter: 100 bars, 400°

C

12 / 45

Applications of High Temperature Electronics

◮ Actuators and electronics close to the jet engine ◮ Deep thermal cycling (-55/+225°

C)

◮ Long operating life (up to 30 years) ◮ Share the cooling system between electrical

and internal combustion engines.

◮ Cooling fluid temperature: 120 °

C

◮ NASA mission to Venus: up to 480°

C

◮ Mission to Jupiter: 100 bars, 400°

C

◮ Oil, gas and geothermal drilling ◮ Low thermal cycling, high ambient temp.

(200 to >300 ° C)

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High temperature behaviour of SiC devices

Static Characterization of 490 mΩ JFET

2 4 6 8 10 12

Forward voltage [V]

2 4 6 8 10 12

Forward current [A]

• 50 ◦ C
• 10 ◦ C

30 ◦ C 70 ◦ C 110 ◦ C 150 ◦ C 190 ◦ C 230 ◦ C 270 ◦ C 300 ◦ C

VGS = 0 V, i.e. device fully-on

◮ Large increase in on-state resistance with temperature; ◮ Strong sensitivity of conduction losses to temperature.

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High temperature behaviour of SiC devices

Static Characterization of 490 mΩ JFET

2 4 6 8 10 12

Forward voltage [V]

2 4 6 8 10 12

Forward current [A]

• 50 ◦ C
• 10 ◦ C

30 ◦ C 70 ◦ C 110 ◦ C 150 ◦ C 190 ◦ C 230 ◦ C 270 ◦ C 300 ◦ C

VGS = 0 V, i.e. device fully-on

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W]

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

◮ Large increase in on-state resistance with temperature; ◮ Strong sensitivity of conduction losses to temperature.

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High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

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High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

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High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

14 / 45

High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

14 / 45

High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

14 / 45

High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

Always stable 14 / 45

High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

Always stable Always unstable 14 / 45

High temperature behaviour of SiC devices

Thermal Run-away mechanism

◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

Always stable Always unstable Becomming unstable with ambient temperature rise 14 / 45

Power dissipation as a function of the junction temp.

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W]

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

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Power dissipation as a function of the junction temp.

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W] 1K/W 2K/W 4.5K/W

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

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High Temperature Thermal Management

Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014

100 150 200 250 300 350 time [s] 30 40 50 60 70 80 power [W]

current changed from 3.65 to 3.7 A Run-away

SiC JFET:

◮ 490 mΩ, 1200 V ◮ RThJA = 4.5 K/W ◮ 135 °

C ambient

◮ On-state losses

High temperature capability = reduced cooling needs! SiC JFETs must be attached to a low-RTh cooling system.

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High Temperature die attaches

The problem with solders

Strengh/Hardness Homologous Temperature

0.4 0.6 1

Properties little affected by temperature Creep range Unable to bear engineering loads Solders operate in this region

Source:

❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴

Homologous temperature: TH = TOper[K] TMelt[K] Example:

◮ AuGe solder: TMelt = 356°

C = 629 K

◮ TH = 0.8 ➜ TOper = 503 K = 230 °

C

◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point:

◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

High Temperature die attaches

The problem with solders

Strengh/Hardness Homologous Temperature

0.4 0.6 1

Properties little affected by temperature Creep range Unable to bear engineering loads Solders operate in this region

Source:

❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴

Homologous temperature: TH = TOper[K] TMelt[K] Example:

◮ AuGe solder: TMelt = 356°

C = 629 K

◮ TH = 0.8 ➜ TOper = 503 K = 230 °

C

◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point:

◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

High Temperature die attaches

The problem with solders

Strengh/Hardness Homologous Temperature

0.4 0.6 1

Properties little affected by temperature Creep range Unable to bear engineering loads Solders operate in this region

Source:

❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴

Homologous temperature: TH = TOper[K] TMelt[K] Example:

◮ AuGe solder: TMelt = 356°

C = 629 K

◮ TH = 0.8 ➜ TOper = 503 K = 230 °

C

◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point:

◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

High Temperature die attaches

The problem with solders

Strengh/Hardness Homologous Temperature

0.4 0.6 1

Properties little affected by temperature Creep range Unable to bear engineering loads Solders operate in this region

Source:

❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴

Homologous temperature: TH = TOper[K] TMelt[K] Example:

◮ AuGe solder: TMelt = 356°

C = 629 K

◮ TH = 0.8 ➜ TOper = 503 K = 230 °

C

◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point:

◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

High Temperature die attaches

The problem with solders

Strengh/Hardness Homologous Temperature

0.4 0.6 1

Properties little affected by temperature Creep range Unable to bear engineering loads Solders operate in this region

Source:

❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴

Homologous temperature: TH = TOper[K] TMelt[K] Example:

◮ AuGe solder: TMelt = 356°

C = 629 K

◮ TH = 0.8 ➜ TOper = 503 K = 230 °

C

◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point:

◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

High Temperature Die Attaches – PhD A. MASSON

◮ development of the

sintering process

◮ Nano-particles paste

from NBE Tech

◮ Evaluation of many parameters

◮ Sintering pressure ◮ Surface roughness ◮ Thickness of stencil ◮ Substrate finish. . .

◮ Once set, process is robust

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High Temperature Die Attaches – PhD A. MASSON

◮ development of the

sintering process

◮ Nano-particles paste

from NBE Tech

◮ Evaluation of many parameters

◮ Sintering pressure ◮ Surface roughness ◮ Thickness of stencil ◮ Substrate finish. . .

◮ Once set, process is robust

10 20 30 40 50 60 70 A’ B C D E F J N O T Shear strenght [MPa] Series name 18 / 45

High Temperature Die Attaches – PhD A. MASSON

◮ development of the

sintering process

◮ Nano-particles paste

from NBE Tech

◮ Evaluation of many parameters

◮ Sintering pressure ◮ Surface roughness ◮ Thickness of stencil ◮ Substrate finish. . .

◮ Once set, process is robust

Ag SiC Cu

10 20 30 40 50 60 70 A’ B C D E F J N O T Shear strenght [MPa] Series name 18 / 45

High Temperature Die Attaches – PhD S. HASCOËT

◮ “Pressureless” sintering process ◮ Based on micro-particles ◮ Findings:

◮ Oxygen is necessary ◮ Bonding on copper (oxide) ◮ Standard Ni/Au finish not ideal ◮ Confirmed by several teams ◮ weak bonds at Ag/Au interface ◮ Bond strength lower ◮ Porosity higher ◮ Can be used to attach fragile components 19 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

200°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

200°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

210°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

210°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

220°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

220°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

230°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

230°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

240°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

240°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

250°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

250°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

260°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

260°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

270°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

270°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

280°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

280°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

290°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

290°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

300°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

300°C

20 / 45

High Temperature Die Attaches

◮ All-sintered assembly ◮ Half-Bridge structure ◮ SiC JFETs ◮ Integrated gate drivers (Ampère) ◮ Ceramic capacitors ◮ Isolation function not integrated

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

310°C

20 / 45

High Temperature Die Attaches – Silver migration, R. RIVA

500 1000 1500 2000 2500 3000 3500 4000 4500 5000 1E-3 1E-2

1/t (h

• 1)

Electric Field (V/mm)

Without parylene Parylene SCS HT

T = 300°C Stop parameter

◮ Causes: electric field, high temperature and oxygen ◮ Large differences between similar test vehicles: ◮ Short life without encapsulation (100–1000 h) ◮ Much longer life with parylene HT protection

21 / 45

High Temperature Die Attaches – Silver migration, R. RIVA

500 1000 1500 2000 2500 3000 3500 4000 4500 5000 1E-3 1E-2

1/t (h

• 1)

Electric Field (V/mm)

Without parylene Parylene SCS HT

T = 300°C Stop parameter

◮ Causes: electric field, high temperature and oxygen ◮ Large differences between similar test vehicles: ◮ Short life without encapsulation (100–1000 h) ◮ Much longer life with parylene HT protection

21 / 45

Conclusion on Packaging for High Temperature

SiC devices can operate at high temperature (>300 ° C)

◮ With efficient thermal management! ◮ RTh must remain low

Silver sintering for high temperature die attaches

◮ Compatible with standard die finishes ◮ Very good results ◮ High thermal/electrical performance ◮ Industry is catching on ◮ Research: long-term behaviour at elevated temperature

◮ pressureless processes are a good model 22 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

22 / 45

New Structures

23 / 45

New Structures

23 / 45

New Structures

23 / 45

New Packaging Structures – Macro post 1

◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link.

24 / 45

New Packaging Structures – Macro post 1

◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link.

24 / 45

New Packaging Structures – Macro post 1

◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link.

24 / 45

New Packaging Structures – Macro post 1

◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link.

24 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

◮ “top” heat-exchanger; ◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

25 / 45

New Packaging Structures – Macro post 1

26 / 45

New Packaging Structures – Macro post 1

10.1 10.2 10.3 time [µs] 100 200 300 400 500 600 700 Vout [V] 11.7 11.8 11.9 time [µs]

◮ Switching speed limited by switches (Si IGBTs, SiC diodes); ◮ No ringing measured at the terminals of the modules; ◮ DC link inductance estimated at 10 nH.

27 / 45

New Packaging Structures – Macro post 2 (R RIVA)

Vbus OUT GND JH JL

◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm×12.7 mm (1 in×0.5 in)

28 / 45

New Packaging Structures – Macro post 2 (R RIVA)

SiC JFET Alumina

0.2 mm

0,3 mm

0.16 mm

0,15 mm

Copper

0.15 mm

Gate Source Source Drain

0.3 mm

Scale drawing for 2.4×2.4 mm2 die

◮ Etching accuracy exceeds

standard design rules

◮ Double-step copper etching for

die contact ➜ Custom etching technique

29 / 45

New Packaging Structures – Macro post 2 (R RIVA)

0.9 1.0 1.1 1.2 time [µs] 50 50 100 150 200 Vout [V] 49.9 50.0 50.1 50.2 time [µs]

200°C

◮ Two-step etching of copper ◮ Ti/Ag PVD using shadow mask on dies ◮ Set of aligment jigs for assembly ◮ Proper drying of silver paste ◮ First electrical tests on 300 Ω load

30 / 45

New Packaging Structures – Macro post 2 (R RIVA)

◮ Good form factor achieved using the two-step copper etching process ◮ Satisfying alignment ◮ Poor quality of Al-Cu attach

31 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

◮ First studies during L. MÉNAGER PhD

◮ Copper posts growth on die (electroplating) ◮ Original die/DBC assembly technology: SnCu diffusion bonding

◮ Proposition of M. SOUEIDAN: direct copper bonding

32 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300°

C

◮ 16 or 77 MPa ◮ Very good bond, without any interface material

◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear

◮ Some investigations performed, much more needed 33 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300°

C

◮ 16 or 77 MPa ◮ Very good bond, without any interface material

◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear

◮ Some investigations performed, much more needed 33 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300°

C

◮ 16 or 77 MPa ◮ Very good bond, without any interface material

◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear

◮ Some investigations performed, much more needed 33 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300°

C

◮ 16 or 77 MPa ◮ Very good bond, without any interface material

◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear

◮ Some investigations performed, much more needed 33 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

5 10 15 20 25 5 10 15 20 25 30 60 90 120 150 180 210 240

◮ “Wafer”-level process ◮ Based on copper electroplating ◮ Assembly of DBC/die/DBC “sandwiches” ◮ No damage to dies

34 / 45

New Packaging Structures – Micro posts (B MOUAWAD)

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Forward Voltage [V] 50 100 150 200 Forward Current [A]

To 247 Sandwich package

◮ Higher resistance than expected

◮ Due to seed layer/die topside interface ◮ Would not happen with suitable dies

◮ Simple and reproducible process

◮ Tens of sample assembled, with good yield

200 300 400 500 600 700 800 Sputter time [s] 2000 4000 6000 8000 10000 12000 14000 16000 Intensity

02 Ti Al2 AlO2 TiO CuO Cu2

35 / 45

Conclusions on New Packaging Structures

◮ Several sandwich configurations:

◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts)

◮ More suited to direct liquid cooling

◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness

◮ Remaining issues:

◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

Conclusions on New Packaging Structures

◮ Several sandwich configurations:

◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts)

◮ More suited to direct liquid cooling

◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness

◮ Remaining issues:

◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

Conclusions on New Packaging Structures

◮ Several sandwich configurations:

◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts)

◮ More suited to direct liquid cooling

◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness

◮ Remaining issues:

◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

36 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

36 / 45

New Packaging Structures for Power Modules

◮ Simulation-based design to evaluate

◮ Thermo-mechanical stress in assemblies (esp. “Sandwiches”) ◮ Thermal resistance ◮ Parasitic inductance/capacitance

◮ Development of structures for fast wide-bandgap devices:

◮ Die stacking (Chip-On-Chip, G2ELab) for low EMI ◮ PCB Embedding 37 / 45

New Packaging Structures for Power Modules

◮ Simulation-based design to evaluate

◮ Thermo-mechanical stress in assemblies (esp. “Sandwiches”) ◮ Thermal resistance ◮ Parasitic inductance/capacitance

◮ Development of structures for fast wide-bandgap devices:

◮ Die stacking (Chip-On-Chip, G2ELab) for low EMI ◮ PCB Embedding

J.-L. Marchesini et al., “Realization and Characterization of an IGBT Module Based on the Power Chip-on-Chip 3D Concept”, ECCE 2014

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power

boards, 2012

37 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project)

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

New Packaging Structures – PCB Embedding

PCB technology offers:

◮ High interconnect density (multilayers, < 50 µm tracks) ◮ Advanced design tools ◮ Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

◮ Silver sintering for accurate positionning of devices ◮ Adaptation of die topside metallization ◮ Advanced DBC etching for thermal management

Flex-based SiC half-bridge interconnect (Industrial project) PCB Embedding, ANR Project ETHAER

38 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

38 / 45

Reliability of High Temperature Packaging

Source: Pressureless Sintering of Microscale Silver Paste for 300° C Applications, Fang Yu et al., IEEE trans. on CMPT, vol. 5, No.9, p 1258–1264

◮ Silver sintered assemblies are increasingly available in the industry ◮ Need to assess its reliability for high temperature

◮ Assessment of migration phenomenon ◮ Next step: effect of atmosphere (oxygen content) ◮ Use of pressureless sintered silver as a material model ◮ Behaviour in high temperature storage conditions ◮ Mechanisms are accelerated and highlighted 39 / 45

Integration in High Temperature

◮ Other elements of packaging:

◮ High temperature ageing of PCBs ◮ Thermo-mechanical analysis of structures ◮ Manufacturing of integrated inductors

(C. MARTIN)

40 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

40 / 45

Packaging of high voltage power devices

◮ Context: Supergrid Institute ◮ Development of HVDC networks ◮ Need for HV devices (>10 kV) and packaging

Source: 10 kV SiC MOSFET from Wolfspeed

◮ Increase in switching speed

◮ Ensure low inductance ◮ Large creepage distance (> 8 cm !)

◮ High conversion efficiency ◮ Trade-off: Insulation/Junction temp.

➜ (Very) efficient cooling required!

41 / 45

Special Features of High Voltage Packaging

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

◮ Series connexions of many switches ◮ A single failed switch should not

stop the converter ➜ Fail-to-short behaviour

◮ For Si dies:

◮ Melting of silicon ◮ Alloying with surrounding metals ◮ Formation of conductive area

◮ SiC only sublimes at > 2500°

C!

42 / 45

Special Features of High Voltage Packaging

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

◮ Series connexions of many switches ◮ A single failed switch should not

stop the converter ➜ Fail-to-short behaviour

◮ For Si dies:

◮ Melting of silicon ◮ Alloying with surrounding metals ◮ Formation of conductive area

◮ SiC only sublimes at > 2500°

C!

42 / 45

Special Features of High Voltage Packaging

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

◮ Series connexions of many switches ◮ A single failed switch should not

stop the converter ➜ Fail-to-short behaviour

◮ For Si dies:

◮ Melting of silicon ◮ Alloying with surrounding metals ◮ Formation of conductive area

◮ SiC only sublimes at > 2500°

C!

42 / 45

Outline

Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion

42 / 45

Conclusion

◮ PhD 11 years ago

◮ From electrical engineering to packaging ◮ 11 PhD students supervised (5 theses defended)

◮ Until recently, most activity on high temperature packaging ◮ Broadening of my research focus

◮ High temperature packaging ◮ High voltage packaging ◮ Integration for WBG devices

◮ Packaging is an active domain

◮ Strong support from the industry ◮ Many scientific challenges 43 / 45

Acknowledgements

cyril.buttay@insa-lyon.fr

44 / 45

Credits

◮ picture of the Airbus A350: airbus ◮ picture of the Toyota Prius: Picture by Pawel Golsztajn, CC-SA,

available on Wikimedia Commons ❤tt♣✿ ✴✴❝♦♠♠♦♥s✳✇✐❦✐♠❡❞✐❛✳♦r❣✴✇✐❦✐✴❋✐❧❡✿❚♦②♦t❛❴Pr✐✉s✳✷✳❏P●

◮ geothermal power plant: ❤tt♣✿✴✴❡♥❡r❣②✳❣♦✈✴❡❡r❡✴

❣❡♦t❤❡r♠❛❧✴♣❤♦t♦s✴❣❡♦t❤❡r♠❛❧✲♣❤♦t♦✲❣❛❧❧❡r②

◮ picture of Jupiter: NASA

❤tt♣✿✴✴❡♥✳✇✐❦✐♣❡❞✐❛✳♦r❣✴✇✐❦✐✴❋✐❧❡✿P■❆✵✹✽✻✻❴♠♦❞❡st✳❥♣❣

45 / 45