GRE Architecture Session Session 2: Saturday 23, 1995 Young H. Cho - - PDF document

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GRE Architecture Session Session 2: Saturday 23, 1995 Young H. Cho - - PDF document

GRE Architecture Session Session 2: Saturday 23, 1995 Young H. Cho e-mail: youngc@cs.berkeley.edu www: http://http.cs.berkeley/~youngc Y. H. Cho Page 1 Review n Homework n Basic Gate Arithmetics n Bubble Pushing n Logic Design n Complex


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SLIDE 1
  • Y. H. Cho

Page 1

GRE Architecture Session

Session 2: Saturday 23, 1995

Young H. Cho

e-mail: youngc@cs.berkeley.edu www: http://http.cs.berkeley/~youngc

  • Y. H. Cho

Page 2

Review

n Homework n Basic Gate Arithmetics n Bubble Pushing n Logic Design n Complex Digital Circuits

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SLIDE 2
  • Y. H. Cho

Page 3

Logic Design & Complex Circuits

n Karnaugh-Map “K-MAP” n Design with 4+ Variables n Debounced Flip-Flop (D-FF) n Culmination of small design concept

  • Y. H. Cho

Page 4

Computer

n What is your idea? n RISC (Reduced Instruction Set

Computer)

n CISC (Complex Instruction Set

Computer)

n RISC versus CISC - Robot arm Analogy

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SLIDE 3
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Page 5

Computer - Parts

n Control n Datapath n Memory n Input n Output

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Page 6

Interconnections

n BUS

  • MBus
  • Mem Bus
  • SCSI
  • External Bus

n Network

  • LAN (Local Area Network)
  • WAN (Wide Area Network)
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SLIDE 4
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Page 7

Memory Hierarchy

n Registers n Cache n Main Memory n Disk n Tape

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Page 8

Performance

n 1 / Execution Time n CPI = Cycles per program/Instruction

Count per Program

n MIPS = Instruction Count / (Time X

10^6) = Clock rate / (CPI X 10^6)

n MFLOPS = Floating point operation /

(Time X 10^6)

n Benchmarks

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SLIDE 5
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Page 9

Benchmarks

n SPEC - System Performance

Evaluation Cooperative

n CPU time = (Instr / Prog) X (Cycles /

Instruction) X (Sec / Cycle)

n Amdahl’s Law

  • Speedup(w/Enhancement) = (Exec Time

without Enh) / (Exec Time with Enh)

  • Y. H. Cho

Page 10

Instruction Set Architecture (ISA)

n Stack

  • operands on top of stack

n Accumulator

  • one operand is implicitly the accumulator

n General Purpose Register n Register/Memory

  • only explicit operands - either memory or

registers

  • acess memory as part of any instruction

n Load/Store

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SLIDE 6
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Page 11

ISA History

n Single Accumulator

  • EDSAC: 1950

n Accumulator + Index Registers

  • Manchester Mark I, IBM 700 series 1953

n Separation of Programming Model from

Implementation

  • High-level Language Based (B5000: 1963)
  • Concept of a Family (IBM 360: 1964)

n General Purpose Register Machines

  • Complex Instruction Sets (VAX Intel 432:
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Page 12

Pipeline

n Laundry Example n Evident Speedup n Patch things up - compiler tricks and

hardware tricks

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SLIDE 7
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Page 13

Basic Technology

n Complementary Metal Oxide Silicon

(CMOS) transistors

  • NMOS

– Turns on when High (Vdd, 5V) is applied – Turns off when Low (Gnd, 0V) is applied – (Analogy: Opens the gate at the hill to let the water flow. Gate controlled by stream of water

  • Water applied to gate controls the gate.)
  • PMOS

– Turns off when High (Vdd, 5V) is applied – Turns on when Low (Gnd, 0V) is applied

  • Y. H. Cho

Page 14

Gate Comparison

n If PMOS transistor is faster: NOR gate

is preferred

  • NMOS in Series
  • PMOS in Parallel
  • H to L is more critical than L to H

n If NMOS transistor is faster: NAND gate

is preferred

  • NMOS in Parallel
  • PMOS in Series
  • L to H is more critical than H to L
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SLIDE 8
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Page 15

Summary

n Performance Measurements n Instruction Set Architecture:

  • Stack
  • Accumulator
  • General Purpose Register:
  • Register/Memory
  • Load/Store
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Page 16

Outline

n Performance n ISA n Technology n ALU n Computer Arithmetics

  • Binary Arithmetics
  • Floating point Arithmetics

n Single cycle and pipelines

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SLIDE 9
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Page 17

Common Sense: 5 Basic Components

n Datapath n Control n Memory n Input n Output

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Page 18

I. Performance

n Comments: Important to Keep this mind

when evaluating benchmarks

n Speedup - Amdahl's Law n Compiler Problem - MIPS and CPI n Equations

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SLIDE 10
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Page 19

  • II. ISA

n Comments: Many different Architecture n Stack n Accumulator n General Purpose Register: n Register/Memory n Load/Store

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Page 20

  • III. Technology

n Comments: Real issue in hardware

implementations

n CMOS technology n Internal Delay n Cycle time

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SLIDE 11
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Page 21

  • IV. Arithmetic Logic Unit (ALU)

n Comments: Basic intelligent unit

implementations

n Carry-Look-Ahead n Carry Select

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Page 22

  • V. Computer Arithmetics

n Binary Standard n Multiplication

  • Booths

n Floating point (IEEE Standard) n Multiply, Shift, and FP Number n Comments: Important to know the

concept

  • IEEE 31 / 30-23 / 22-0
  • (-1)^s * (1+significand) x 2^(exponent-bias)
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SLIDE 12
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Page 23

  • VI. Single Cycle and Pipeline

Datapath

n Datapath n Draw your idea of what Computer is n Block diagram