GraVF: GraVF: A Vertex-Centric A Vertex-Centric Graph Processing - - PowerPoint PPT Presentation

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Jul 17, 2023 165 likes •264 views

GraVF: GraVF: A Vertex-Centric A Vertex-Centric Graph Processing Graph Processing Framework Framework on FPGA on FPGA Nina Engelhardt August 31, 2016 Graphs and Graph Traversal Algorithms 1 Vertex-centric Programming Model: From POV of

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GraVF: GraVF: A Vertex-Centric A Vertex-Centric Graph Processing Graph Processing Framework Framework

n FPGA
n FPGA

Nina Engelhardt

August 31, 2016

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Graphs and Graph Traversal Algorithms

Vertex-centric Programming Model: From POV of an individual vertex Receive messages from neighbors, calculate, send messages to neighbors Global barrier after each iteration

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Synchronous Vertex-centric Programming Model

Advantages: naturally distributed

nly very short kernel to write

Challenges: barrier means stragglers can unduly delay whole computation have to store all messages from one superstep to the next → Floating barrier [1]: PE broadcasts barrier message when it finishes superstep, allowing overlapping of supersteps

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Architecture modifications

PE PE ... PE PE PE ... PE ... PE PE ... PE ... ... ...

Apply Kernel Apply Scatter Vertex Storage Edge Storage Scatter Kernel update queue

PE

Split Vertex Kernel in 2 phases: Apply and Scatter Everything is pipelined: free to move registers

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Barrier Synchronization

PE0

Scatter update queue Apply Arbiter from PE 0 from PE 1 ... from PE n-1 barrier message for superstep i message for superstep i+1

Apply ahead of Scatter: messages processed immediately update queue only 2|V | entries instead of |V |2

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Results

200 400 600 800 1000 1200 1400 1600 1 2 4 8 16 x1000 Cycles Number of PEs Weak Scaling PR BFS 5 10 15 20 25 12 4 8 16 32 Edges traversed per cycle Number of PEs Strong Scaling PR BFS

3-3.5 GTEPS: comparable to hand-implemented solutions

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Future Work

Extend communication to multiple FPGA boards Include data transfers: direct SSD access from FPGA

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SLIDE 8

Thank you for listening

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Works Cited I

1Betweenness Centrality; By Claudio Rocchini, CC BY 2.5,

https://commons.wikimedia.org/w/index.php?curid=1988980

Qingbo Wang, Weirong Jiang, Yinglong Xia, and V. Prasanna. A message-passing multi-softcore architecture on FPGA for breadth-first search. In Field-Programmable Technology (FPT), 2010 International Conference on, pages 70–77, Dec 2010.

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