Functional Design Using Behavioural and Structural Components - - PowerPoint PPT Presentation

Functional Design Using Behavioural and Structural Components

Richard Sharp

rws26@cl.cam.ac.uk

University of Cambridge

aims of this research

SAFL is a Behavioural HDL

• Supports a functional programming style
• Designed for source-level program transformation
• Ease of analysis and optimisation

Combine behaviour and structure?

• Verilog/VHDL do this to great effect… but as a result

are very complex => transformation VERY difficult.

Aim: to combine behavioural- and structural-level design elements in a pure-functional framework. Aim: to combine behavioural- and structural-level design elements in a pure-functional framework.

talk

• verview

Behavioural HDL: SAFL Structural HDL: Magma Integrating SAFL + Magma Case Study Conclusions and further work

SAFL: a behavioural HDL

Functional Call-by-value First-order Functional Call-by-value First-order

statically allocated functional language

The FLaSH Silicon Compiler translates SAFL into RTL-Verilog. The FLaSH Silicon Compiler translates SAFL into RTL-Verilog.

Concurrent Statically Allocated Resource Aware Concurrent Statically Allocated Resource Aware

General properties Hardware-specific properties

Other tools (e.g. Leonardo Spectrum, Quartus II, Modelsim) process this RTL-Verilog and map it onto silicon. Other tools (e.g. Leonardo Spectrum, Quartus II, Modelsim) process this RTL-Verilog and map it onto silicon.

a SAFL example

mult f cube

fun mult(x, y, acc) = if (x=0 | y=0) then acc else mult(x<<1, y>>1, if y[0] then acc+x else acc) fun cube(x) = mult(x, mult(x, x, 0), 0) fun f(x) = let val y=mult(x,5,0) in y+x end circuit structure:

• Behavioural, … but
• … captures system-level structure
• One “fun definition” => one hardware

resource SAFL Properties

magma: a structural HDL

Embedded in pure-functional ML

• Similar syntax and semantics (CBV) to SAFL

Supports synthesis/simulation

• Uses ML functors to parameterise over different basis

functions

• Synthesis == Static Expansion

Only describes acyclic, combinatorial hardware

• no “observable sharing” problems

a magma example (1)

functor RippleAdder (B:BASIS):RP_ADD = struct type bit=B.bit fun adder (x,y,c_in) = (B.xorb(c_in, B.xorb(x,y)), B.orb( B.orb( B.andb (x,y), B.andb(x,c_in)), B.andb(y,c_in)))

Adder c_in x y c_out s_out

a magma example (2)

fun carry_chain f _ ([],[]) = [] | carry_chain f c_in (x::xs,y::ys) = let val (res_bit, c_out) = f (x,y,c_in) in res_bit::(carry_chain f c_out (xs,ys)) end val ripple_add = carry_chain adder B.b0

Adder x1 y1 b0 Adder x2 y2 Adder x3 y3 Adder Adder X4 y4 x5 y5 s_out1 s_out2 s_out3 s_out4 s_out5

a magma example (3)

• structure SimulateAdder = RippleAdder (SimulationBasis);
• SimulateAdder.ripple_add ([b1,b0,b0,b1,b1,b1],[b0,b1,b1,b0,b1,b1])

val it = [b1,b1,b1,b1,b0,b1] : SimulateAdder.bit list

• structure SynthesiseAdder = RippleAdder (SynthesisBasis);
• SynthesiseAdder.ripple_add (Magma.new_bus 5, Magma.new_bus 5)

and(w_1,w_45,w_46); and(w_2,w_1,w_44); ... and(w_149,w_55,w_103); val it = ["w_149","w_150","w_151","w_152","w_153"]

Support for simulation and synthesis:

integrating SAFL and magma (1)

<% (* Magma code Library Block: ---------------------------------- *) signature RP_ADD = ... functor Magma_Code (B:BASIS):RP_ADD = ... Contains ripple adder spec (as before) %> (* SAFL code: ------------------------------------------------- *) fun mult(x, y, acc) = if (x=0 | y=0) then acc else mult(x<<1, y>>1, if y[0] then <% ripple_add %>(acc,x) else acc)

• Magma fragments treated as SAFL-level functions

integrating SAFL and magma (2)

Encounter Magma Fragment Execute Magma under Synthesis Interpretation

Process 2: SAFL Compiler Process 1: ML Session

Magma Verilog [Time]

<% m %>(e_1, …, e_k)

integrating SAFL and magma (3)

fun f(x) = <% M %>(x) + <% M %>(x) fun g(x) = <% M %>(x) fun f(x) = g(x) + g(x) RTL Verilog FPGA Source-level transformation High-level synthesis RTL synthesis

case study: DES

SAFL Describes DES Algorithm Magma Describes Wiring Permutations Current Version Not Pipelined

• Making a pipelined version through SAFL/Magma program

transformation is topic of future work Throughput of 15.8 Mb/sec

• On Altera APEX 200K FPGA with 33MHz clock
• Theoretical max clock speed design > 40MHz

2 DES blocks + test harness => 17% of FPGA

case study: DES – Dev Boad

APEX E20K200E Status LEDs

conclusions

It is possible to combine behavioural +

(limited) structural design in a clean way

Fine-grained structure integrates well

with SAFL’s notion of resource-awareness

Program transformation remains a

powerful technique for exploring tradeoffs

Tested technique on a real-life case study

• ngoing

research

Extending the SAFL Language

• ML-style references
• Many-many synchronous channels
• Pi-calculus style channel passing

Extending the FLaSH tool-chain

• Developing / experimenting with new SAFL

transformations

• Building SAFL compiler which targets asynchronous

hardware

Building larger examples