Finding a Needle in the Haystack of Hardened Interconnect Patterns - - PowerPoint PPT Presentation
Finding a Needle in the Haystack of Hardened Interconnect Patterns S. Nikoli, G. Zgheib*, and P. Ienne FPL19, Barcelona, 09.09.2019 cole Polytechnique Fdrale de Lausanne *Intel Corporation Why harden connections? 2 crossbar LUT LUT
FPL19, Barcelona, 09.09.2019
École Polytechnique Fédérale de Lausanne *Intel Corporation
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Cluster architecture Circuit to be mapped 3
XC4000 [1] Triptych [3] UTFPGA1 [2]
[1] H.-C. Hsieh, W. S. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin,
density of field-programmable gate arrays, 1990 [2] P. Chow, S. O. Seo, D. Au, B. Fallah, C. Li, and J. Rose. A 1.2um CMOS FPGA using cascaded logic blocks and segmented routing, 1991 [3] C. Ebeling, G. Borriello, S. A. Hauck, D. Song, E. A. Walkup. TRIPTYCH: A New FPGA Architecture, 1991
How to design the patterns?
How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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How to design the patterns?
How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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How to design the patterns?
How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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How to design the patterns?
How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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How to design the patterns?
How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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I I LUT LUT LUT LUT LUT LUT
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I I LUT LUT LUT LUT LUT LUT
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I I LUT LUT LUT LUT LUT LUT
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I I LUT LUT LUT LUT LUT LUT
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I I LUT LUT LUT LUT LUT LUT
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//V - vertex set G = (V, {}) expandable = (G) while expandable { G = pop(expandable) for e in V x V { if keep(G + e) { push(G + e, expandable) } } }
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//V - vertex set G = (V, {}) expandable = (G) while expandable { G = pop(expandable) for e in V x V { if keep(G + e) { push(G + e, expandable) } } }
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//V - vertex set G = (V, {}) expandable = (G) while expandable { G = pop(expandable) for e in V x V { if keep(G + e) { push(G + e, expandable) } } }
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//V - vertex set G = (V, {}) expandable = (G) while expandable { G = pop(expandable) for e in V x V { if keep(G + e) { push(G + e, expandable) } } }
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When area or delay stop decreasing? When area or delay start increasing?
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When area or delay stop decreasing? When area or delay start increasing?
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LUT LUT LUT Circuit to be mapped No hardened connections
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LUT LUT LUT
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LUT LUT LUT Circuit to be mapped No hardened connections With hardened connections
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LUT LUT LUT
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LUT LUT LUT Circuit to be mapped No hardened connections With hardened connections
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LUT LUT LUT
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LUT LUT LUT LUT LUT LUT Circuit to be mapped No hardened connections With hardened connections
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LUT LUT LUT
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LUT LUT LUT LUT LUT LUT Circuit to be mapped No hardened connections With hardened connections When area or delay start increasing? When area or delay stop decreasing?
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G H2 H1
x y z
xx xy xz yy yz zz
xxx xxy xxz xyy xyz xzz yyy yyz yzz zzz
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How to design the patterns?
5 5-LUT 108 How to map on patterns? (CAD tool scalability)
LUT LUT LUT LUT LUT 12
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( 108 patterns)
(20 5-LUT clusters)
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( 108 patterns)
(20 5-LUT clusters)
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( 108 patterns)
(20 5-LUT clusters)
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b e a c d
Some examples
Found 261 patterns with only 12 external inputs achieving 80% packing density
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blob_merge boundtop ch_intrinsics diffeq1 diffeq2 mkDelayWorker32B mkPktMerge mkSMAdapter4B
raygentop sha stereovision0 stereovision1 stereovision3 65 70 75 80 85 90 95 utilization [%]
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Numerical results not satisfactory (18-29% critical path delay increase) But... We have an efficient way of searching for good patterns
mapping algorithms In the future, this should help us understand what makes a good pattern and profit from connection hardening to the fullest
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